IMX53CEC datasheet(107/204 Pages) FREESCALE

107 / 204 page

Electrical Characteristics

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

107

4.7.9

LVDS Display Bridge (LDB) Module Parameters

The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD

644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”.

4.7.10

One-Wire (OWIRE) Timing Parameters

Figure 58 depicts the RPP timing, and Table 66 lists the RPP timing parameters.

Figure 58. Reset and Presence Pulses (RPP) Timing Diagram

7Display control down for read

DISP_DOWN is predefined in REGISTER.

8Display control up for write

DISP_UP is predefined in REGISTER.

Table 66. RPP Sequence Delay Comparisons Timing Parameters

Parameters

Symbol

Min

Typ

Max

Unit

OW1

Reset Time Low

tRSTL

480

511

—1

1 In order not to mask signaling by other devices on the 1-Wire bus, t

RSTL + tR should always be less than 960 µs.

µs

OW2

Presence Detect High

tPDH

—

µs

OW3

Presence Detect Low

tPDL

—

240

µs

OW4

Reset Time High

(includes recovery time)

tRSTH

480

512

—

µs

Tdicdrw

---T

DI_CLK

ceil

DISP_DOWN_#

DI_CLK_PERIOD

--------------------------------------------------

⎝⎠

⎛⎞

Tdicuw

---T

DI_CLK

ceil

2DISP_UP_#

DI_CLK_PERIOD

----------------------------------------------

⎝⎠

⎛⎞

One-Wire bus

One Wire Device Tx

“Presence Pulse”

(BATT_LINE)

One-WIRE Tx

“Reset Pulse”

OW1

OW2

OW3

OW4

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