ADSP-BF504 datasheet(28/80 Pages) AD

28 / 80 page

Rev. PrC

Page 28 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

IDDFLASH4

Flash Memory Supply Current 4

— Automatic Standby

μA

IDDFLASH5

Flash Memory Supply Current 5

— Program

Flash Memory Supply Current 5

— Erase

IDDFLASH6

Flash Memory Supply Current 6

— Dual Operations

Program/Erase in one bank,

asynchronous read in

another bank

Program/Erase in one bank,

synchronous read in another

bank

IDDFLASH7

Flash Memory Supply Current 7

— Program/Erase Suspended (Standby)

μA

1 Applies to input pins.

2 Applies to JTAG input pins (TCK, TDI, TMS, TRST).

3 Applies to three-statable pins.

4 Applies to bidirectional pins SCL and SDA.

5 Applies to all signal pins.

6 Guaranteed, but not tested.

7 See the ADSP-BF50x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.

8 Applies to VDDEXT supply only. Clock inputs are tied high or low.

9 Guaranteed maximum specifications.

10Unit for VDDINT is V (Volts). Unit for fSCLK is MHz. Example: TBD V, TBD MHz would be TBD x TBD x TBD = TBD mA adder.

11See the ADSP-BF50x Blackfin Processor Hardware Reference Manual for definition of NORCLK.

Parameter

Test Conditions

Min

Typical

Max

Unit

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