ADSP-BF504 datasheet(45/80 Pages) AD

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Preliminary Technical Data

Rev. PrC

Page 45 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Timer Clock Timing

Table 36 and Figure 25 describe timer clock timing.

Up/Down Counter/Rotary Encoder Timing

Table 36. Timer Clock Timing

Parameter

DDEXT = 1.8 V

DDEXT = 2.5/3.3 V

Min

Max

Min

Max

Unit

Switching Characteristic

tTODP

Timer Output Update Delay After PPI_CLK High

12.0

Figure 25. Timer Clock Timing

Table 37. Up/Down Counter/Rotary Encoder Timing

Parameter

DDEXT = 1.8 V

DDEXT = 2.5/3.3 V

Min

Max

Min

Max

Unit

Timing Requirements

tWCOUNT

Up/Down Counter/Rotary Encoder Input Pulse Width

tSCLK + 1

tCIS

Counter Input Setup Time Before CLKOUT High

1 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.

5.5

4.0

tCIH

Counter Input Hold Time After CLKOUT High

4.0

Figure 26. Up/Down Counter/Rotary Encoder Timing

PPI_CLK

TMRx OUTPUT

tTODP

CLKOUT

CUD/CDG/CZM

tCIS

tCIH

tWCOUNT

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