ADSP-BF504 datasheet(62/80 Pages) AD

62 / 80 page

Rev. PrC

Page 62 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

When the ADC starts a conversion (see Figure 69 (ADC Con-

version Phase)), SW3 opens and SW1 and SW2 move to

Position B, causing the comparator to become unbalanced. Both

inputs are disconnected once the conversion begins. The con-

trol logic and the charge redistribution DACs are used to add

and subtract fixed amounts of charge from the sampling capaci-

tor arrays to bring the comparator back into a balanced

condition. When the comparator is rebalanced, the conversion

is complete. The control logic generates the ADC output code.

The output impedances of the sources driving the VIN+ and VIN–

pins must be matched; otherwise, the two inputs will have dif-

ferent settling times, resulting in errors.

Analog Input Structure

Figure 70 (Equivalent Analog Input Circuit, Conversion

Phase—Switches Open, Track Phase—Switches Closed) shows

the equivalent circuit of the analog input structure of the ADC

in differential/pseudo differential mode. In single-ended mode,

VIN is internally tied to AGND. The four diodes provide ESD

protection for the analog inputs. Care must be taken to ensure

that the analog input signals never exceed the supply rails by

more than 300 mV. This causes these diodes to become for-

ward-biased and starts conducting into the substrate. These

diodes can conduct up to 10 mA without causing irreversible

damage to the part.

The C1 capacitors in Figure 70 (Equivalent Analog Input Cir-

cuit, Conversion Phase—Switches Open, Track Phase—

Switches Closed) are typically 4 pF and can primarily be attrib-

uted to pin capacitance. The resistors are lumped components

made up of the on resistance of the switches. The value of these

resistors is typically about 100

Ω. The C2 capacitors are the

ADC’s sampling capacitors with a capacitance of 45 pF typically.

For ac applications, removing high frequency components from

the analog input signal is recommended by the use of an RC

low-pass filter on the relevant analog input pins with optimum

values of 47

Ω and 10 pF. In applications where harmonic dis-

tortion and signal-to-noise ratio are critical, the analog input

should be driven from a low impedance source. Large source

impedances significantly affect the ac performance of the ADC

and may necessitate the use of an input buffer amplifier. The

choice of the op amp is a function of the particular application.

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance depends on the amount of THD that can be

tolerated.

The THD increases as the source impedance increases and per-

formance degrades. Figure 71 (THD vs. Analog Input

Frequency for Various Source Impedances, Single-Ended Mode

shows a graph of the THD vs. the analog input signal frequency

for different source impedances in single-ended mode, while

Figure 72 (THD vs. Analog Input Frequency for Various Source

Impedances, Differential Mode) shows the THD vs. the analog

input signal frequency for different source impedances in differ-

ential mode.

Figure 73 (THD vs. Analog Input Frequency for Various Supply

Voltages) shows a graph of the THD vs. the analog input fre-

quency for various supplies while sampling at 2 MSPS. In this

case, the source impedance is 47

Ω.

Figure 69. ADC Conversion Phase

Figure 70. Equivalent Analog Input Circuit,

Conversion Phase—Switches Open, Track Phase—Switches Closed

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

SW2

VIN+

VIN–

VREF

VDD

VIN+

R1 C2

VDD

VIN–

R1 C2

Figure 71. THD vs. Analog Input Frequency for Various

Source Impedances, Single-Ended Mode

INPUT FREQUENCY (kHz)

600

200

100

400

300

500

–50

–60

–55

–65

–70

–75

–80

–85

–90

FSAMPLE = 1.5MSPS

VDD = 3V

RANGE = 0V TO VREF

RSOURCE = 300

RSOURCE = 0

RSOURCE = 10

RSOURCE = 47

RSOURCE = 100

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