ADSP-BF504 datasheet(44/80 Pages) AD

44 / 80 page

Rev. PrC

Page 44 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

Timer Cycle Timing

Table 35 and Figure 24 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and

“external clock mode” and has an absolute maximum input fre-

quency of (fSCLK/2) MHz.

Table 35. Timer Cycle Timing

Parameter

DDEXT = 1.8 V

DDEXT = 2.5/3.3 V

Min

Max

Min

Max

Unit

Timing Requirements

tWL

Timer Pulse Width Input Low

(Measured In SCLK Cycles)

1 × tSCLK

tWH

Timer Pulse Width Input High

(Measured In SCLK Cycles)1

1 × tSCLK

tTIS

Timer Input Setup Time Before CLKOUT Low

55ns

tTIH

Timer Input Hold Time After CLKOUT Low

–2

Switching Characteristics

tHTO

Timer Pulse Width Output

(Measured In SCLK Cycles)

1 × tSCLK

(232–1)tSCLK

1 × tSCLK

(232–1)tSCLK

tTOD

Timer Output Update Delay After CLKOUT High

8.1

1 The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PG0 or PPI_CLK signals in PWM output mode.

2 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.

Figure 24. Timer Cycle Timing

CLKOUT

TMRx OUTPUT

TMRx INPUT

tTIS

tTIH

tWH,tWL

tTOD

tHTO

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