ADSP-BF504 datasheet(46/80 Pages) AD

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46 / 80 page

Rev. PrC

Page 46 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

Pulse Width Modulator (PWM) Timing

Table 38 and Figure 27 describe PWM operations.

Table 38. PWM Timing

Parameter

DDEXT = 1.8 V

DDEXT = 2.5/3.3 V

Min

Max

Min

Max

Unit

Timing Requirements

tES

External Sync Pulse Width

2 × tSCLK + 1

Switching Characteristics

tDODIS

Output1 Inactive (OFF) After Trip Input

TBD

tDOE

Output

1 Delay After External Sync2

3 × tSCLK + tOD

5 × tSCLK + tOD

3 × tSCLK + tOD

5 × tSCLK + tOD

tOD

Output

1 Delay After Falling Edge of CLKOUT

TBD

1 PWM outputs are: PWMx_AH, PWMx_AL, PWMx_BH, PWMx_BL, PWMx_CH, and PWMx_CL.

2 When the external sync signal is synchronous to the peripheral clock, it takes 3 cycles for the output to appear. When the external sync signal is asynchronous to the peripheral

clock, it takes 5 cycles for the output to appear.

Figure 27. PWM Timing

PWMx_TRIP

PWMx_SYNC

(AS INPUT)

tES

tDOE

OUTPUT

tOD

tDODIS

CLKOUT

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