ADSP-BF504 datasheet(20/80 Pages) AD

20 / 80 page

Rev. PrC

Page 20 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

ADC APPLICATION HINTS

The following sections provide application hints for using the

ADC.

Grounding and Layout Considerations

The analog and digital supplies to the ADC are independent and

separately pinned out to minimize coupling between the analog

and digital sections of the device. The printed circuit board

(PCB) that houses the ADC should be designed so that the ana-

log and digital sections are separated and confined to certain

areas of the board. This design facilitates the use of ground

planes that can be easily separated.

To provide optimum shielding for ground planes, a minimum

etch technique is generally best. All AGND pins should be sunk

in the AGND plane. Digital and analog ground planes should be

joined in only one place. If the ADC is in a system where multi-

ple devices require an AGND to DGND connection, the

connection should still be made at one point only, a star ground

point that should be established as close as possible to the

ground pins on the ADC.

Avoid running digital lines under the device as this couples

noise onto the die. Avoid running digital lines in the area of the

AGND pad as this couples noise onto the ADC die and into the

AGND plane. The power supply lines to the ADC should use as

large a trace as possible to provide low impedance paths and

reduce the effects of glitches on the power supply line.

To avoid radiating noise to other sections of the board, fast

switching signals, such as clocks, should be shielded with digital

ground, and clock signals should never run near the analog

inputs. Avoid crossover of digital and analog signals. To reduce

the effects of feed through within the board, traces on opposite

sides of the board should run at right angles to each other.

Good decoupling is also important. All analog supplies should

be decoupled with 10 μF tantalum capacitors in parallel with 0.1

μF capacitors to GND. To achieve the best results from these

decoupling components, they must be placed as close as possible

to the device, ideally right up against the device. The 0.1 μF

capacitors should have low effective series resistance (ESR) and

effective series inductance (ESI), such as the common ceramic

types or surface-mount types. These low ESR and ESI capacitors

provide a low impedance path to ground at high frequencies to

handle transient currents due to internal logic switching.

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