KM416RD8AS-RBM80 datasheet(24/64 Pages) SAMSUNG

24 / 64 page

Page 21

KM416RD8AS

Direct RDRAM™

Rev. 0.9 July 1999

Target

Write Transaction - Example

Figure 16 shows an example of a write transaction. It begins

by activating a bank with an ACT a0 command in an ROWA

packet. A time tRCD-tRTR later a WR a1 command is issued

in a COLC packet (note that the tRCD interval is measured to

the end of the COLC packet with the first retire command).

Note that the ACT command includes the device, bank, and

row address (abbreviated as a0) while the WR command

includes device, bank, and column address (abbreviated as

a1). A time tCWD after the WR command the write data

dualoct D(a1) is issued. Note that the packets on the ROW

and COL pins use the end of the packet as a timing reference

point, while the packets on the DQA/DQB pins use the

beginning of the packet as a timing reference point.

A time tCC after the first COLC packet on the COL pins a

second COLC packet is issued. It contains a WR a2

command. The a2 address has the same device and bank

address as the a1 address (and a0 address), but a different

column address. A time tCWD after the second WR

command a second write data dualoct D(a2) is issued.

A time tRTR after each WR command an optional COLM

packet MSK (a1) is issued, and at the same time a COLC

packet is issued causing the write buffer to automatically

retire. See Figure 17 for more detail on the write/retire

mechanism. If a COLM packet is not used, all data bytes are

unconditionally written. If the COLC packet which causes

the write buffer to retire is delayed, then the COLM packet

(if used) must also be delayed.

Next, a PRER a3 command is issued in an ROWR packet on

the ROW pins. This causes the bank to precharge so that a

different row may be activated in a subsequent transaction or

so that an adjacent bank may be activated. The a3 address

includes the same device and bank address as the a0, a1, and

a2 addresses. The PRER command must occur a time tRAS

or more after the original ACT command (the activation

operation in any DRAM is destructive, and the contents of

the selected row must be restored from the two associated

sense amps of the bank during the tRAS interval).

A PRER a3 command is issued in an ROWR packet on the

ROW pins. The PRER command must occur a time tRTP or

more after the last COLC which causes an automatic retire.

Finally, an ACT b0 command is issued in an ROWR packet

on the ROW pins. The second ACT command must occur a

time tRC or more after the first ACT command and a time tRP

or more after the PRER command. This ensures that the

bank and its associated sense amps are precharged. This

example assumes that the second transaction has the same

device and bank address as the first transaction, but a

different row address. Transaction b may not be started until

transaction a has finished. However, transactions to other

banks or other devices may be issued during transaction a.

Figure 16: Write Transaction Example

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T24

T28

T17

T21

T25

T29

T18

T22

T26

T30

T19

T23

T27

T31 T32

T36

T40

T44

T33

T37

T41

T45

T34

T38

T42

T46

T35

T39

T43

T47

MSK (a2)

retire (a2)

MSK (a1)

retire (a1)

WR a1

PRER a3

WR a2

D (a2)

tRCD

D (a1)

ACT b0

tRC

tRP

ACT a0

tCWD

Transaction a: WR

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a2 = {Da,Ba,Ca2}

a3 = {Da,Ba}

tCC

tCWD

tRTR

tRAS

tRTR

tRTP

Transaction b: xx

b0 = {Da,Ba,Rb}

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