KM416RD8AS-RBM80 datasheet(62/64 Pages) SAMSUNG

62 / 64 page

Page 59

KM416RD8AS

Direct RDRAM™

Rev. 0.9 July 1999

Target

Glossary of Terms

ACT

Activate command from AV field.

activate

To access a row and place in sense amp.

adjacent

Two RDRAM banks which share sense

amps (also called doubled banks).

ASYM

CCA register field for RSL VOL/VOH.

ATTN

Power state - ready for ROW/COL

packets.

ATTNR

Power state - transmitting Q packets.

ATTNW

Power state - receiving D packets.

Opcode field in ROW packets.

bank

A block of 2RBIT•2 CBITstorage cells in the

core of the RDRAM.

Bank address field in COLC packet.

BBIT

CNFGA register field - # bank address

bits.

broadcast

An operation executed by all RDRAMs.

Bank address field in ROW packets.

bubble

Idle cycle(s) on RDRAM pins needed

because of a resource constraint.

BYT

CNFGB register field - 8/9 bits per byte.

Bank address field in COLX packet.

Column address field in COLC packet.

CAL

Calibrate (IOL) command in XOP field.

CBIT

CNFGB register field - # column address

bits.

CCA

Control register - current control A.

CCB

Control register - current control B.

CFM,CFMN

Clock pins for receiving packets.

Channel

ROW/COL/DQ pins and external wires.

CLRR

Clear reset command from SOP field.

CMD

CMOS pin for initialization/power control.

CNFGA

Control register with configuration fields.

CNFGB

Control register with configuration fields.

COL

Pins for column-access control.

COL

COLC,COLM,COLX packet on COL pins.

COLC

Column operation packet on COL pins.

COLM

Write mask packet on COL pins.

column

Rows in a bank or activated row in sense

amps have 2CBIT dualocts column storage.

command

A decoded bit-combination from a field.

COLX

Extended operation packet on COL pins.

controller

A logic-device which drives the

ROW/COL /DQ wires for a Channel of

RDRAMs.

COP

Column opcode field in COLC packet.

core

The banks and sense amps of an RDRAM.

CTM,CTMN

Clock pins for transmitting packets.

current control

Periodic operations to update the proper

IOL value of RSL output drivers.

Write data packet on DQ pins.

DBL

CNFGB register field - doubled-bank.

Device address field in COLC packet.

device

An RDRAM on a Channel.

DEVID

Control register with device address that is

matched against DR, DC, and DX fields.

Device match for ROW packet decode.

doubled-bank

RDRAM with shared sense amp.

DQA and DQB pins.

DQA

Pins for data byte A.

DQB

Pins for data byte B.

DQS

NAPX register field - PDN/NAP exit.

DR,DR4T,DR4F

Device address field and packet framing

fields in ROWA and ROWR packets.

dualoct

16 bytes - the smallest addressable datum.

Device address field in COLX packet.

field

A collection of bits in a packet.

INIT

Control register with initialization fields.

initialization

Configuring a Channel of RDRAMs so

they are ready to respond to transactions.

LSR

CNFGA register field - low-power self-

refresh.

Mask opcode field (COLM/COLX packet).

Field in COLM packet for masking byte A.

Field in COLM packet for masking byte B.

MSK

Mask command in M field.

MVER

Control register - manufacturer ID.

NAP

Power state - needs SCK/CMD wakeup.

NAPR

Nap command in ROP field.

NAPRC

Conditional nap command in ROP field.

NAPXA

NAPX register field - NAP exit delay A.

NAPXB

NAPX register field - NAP exit delay B.

NOCOP

No-operation command in COP field.

NOROP

No-operation command in ROP field.

KM416RD8AS-RBM80 bảng dữ liệu(PDF) 62 Page - Samsung semiconductor

KM416RD8AS-RBM80 bảng dữ liệu(HTML) 62 Page - Samsung semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

bảng dữ liệu tải về

Link URL