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KM416RD8AS-RBM80 bảng dữ liệu(PDF) 50 Page - Samsung semiconductor |
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KM416RD8AS-RBM80 bảng dữ liệu(HTML) 50 Page - Samsung semiconductor |
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50 / 64 page  Page 47 KM416RD8AS Direct RDRAM™ Rev. 0.9 July 1999 Target RSL - Clocking Figure 53 is a timing diagram which shows the detailed requirements for the RSL clock signals on the Channel. The CTM and CTMN are differential clock inputs used for transmitting information on the DQA and DQB, outputs. Most timing is measured relative to the points where they cross. The tCYCLE parameter is measured from the falling CTM edge to the falling CTM edge. The tCL and tCH param- eters are measured from falling to rising and rising to falling edges of CTM. The tCR and tCF rise- and fall-time parame- ters are measured at the 20% and 80% points. The CFM and CFMN are differential clock outputs used for receiving information on the DQA, DQB, ROW and COL outputs. Most timing is measured relative to the points where they cross. The tCYCLE parameter is measured from the falling CFM edge to the falling CFM edge. The tCL and tCH parameters are measured from falling to rising and rising to falling edges of CFM. The tCR and tCF rise- and fall-time parameters are measured at the 20% and 80% points. The tTR parameter specifies the phase difference that may be tolerated with respect to the CTM and CFM differential clock inputs (the CTM pair is always earlier). Figure 53: RSL Timing - Clock Signals VCIH 50% VCIL 80% 20% CTM CTMN VCIH 50% VCIL 80% 20% CFM CFMN tTR tCF tCF tCR tCR tCYCLE tCL tCH tCF tCF tCR tCR tCYCLE tCL tCH VCM VX+ VX- VCM VX+ VX- |
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