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KM416RD8AS-RBM80 bảng dữ liệu(PDF) 51 Page - Samsung semiconductor

tên linh kiện KM416RD8AS-RBM80
Giải thích chi tiết về linh kiện  128Mbit RDRAM 256K x 16 bit x 2*16 Dependent Banks Direct RDRAMTM for Consumer Package
PDF  64 Pages
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nhà sản xuất  SAMSUNG [Samsung semiconductor]
Trang chủ  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM416RD8AS-RBM80 bảng dữ liệu(HTML) 51 Page - Samsung semiconductor

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Page 48
KM416RD8AS
Direct RDRAM™
Rev. 0.9July 1999
Target
RSL - Receive Timing
Figure 54 is a timing diagram which shows the detailed
requirements for the RSL input signals on the Channel.
The DQA, DQB, ROW, and COL signals are inputs which
receive information transmitted by a Direct RAC on the
Channel. Each signal is sampled twice per tCYCLE interval.
The set/hold window of the sample points is tS/tH. The
sample points are centered at the 0% and 50% points of a
cycle, measured relative to the crossing points of the falling
CFM clock edge. The set and hold parameters are measured
at the VREF voltage point of the input transition.
The tDR and tDF rise- and fall-time parameters are measured
at the 20% and 80% points of the input transition.
Figure 54: RSL Timing - Data Signals for Receive
VDIH
VREF
VDIL
80%
20%
VCIH
50%
VCIL
80%
20%
CFM
CFMN
DQA
tS
ROW
DQB
tDF
tDR
tH
tS
tH
0.5•t CYCLE
even
odd
COL
VCM
VX+
VX-



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