SPMC68CK338CPV14 datasheet(67/133 Pages) FREESCALE

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MC68CK338

MOTOROLA

MC68CK338TS/D

CPOL — Clock Polarity

0 = The inactive state value of SCK is logic level zero.

1 = The inactive state value of SCK is logic level one.

CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with CPHA to

produce a desired clock/data relationship between master and slave devices.

CPHA — Clock Phase

0 = Data is captured on the leading edge of SCK and changed on the following edge of SCK.

1 = Data is changed on the leading edge of SCK and captured on the following edge of SCK.

CPHA determines which edge of SCK causes data to change and which edge causes data to be cap-

tured. CPHA is used with CPOL to produce a desired clock/data relationship between master and slave

devices. CPHA is set at reset.

SPBR[7:0] — Serial Clock Baud Rate

The QSPI uses a modulus counter to derive SCK baud rate from the MCU system clock. Baud rate is

selected by writing a value from 2 to 255 into the SPBR[7:0] field. The following equation determines

the SCK baud rate:

Giving SPBR[7:0] a value of zero or one disables the baud rate generator. SCK is disabled and as-

sumes its inactive state value. No serial transfers occur. At reset, baud rate is initialized to one eighth

of the system clock frequency.

SPCR1 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write

this register, but the QSM has read access only, except for SPE, which is automatically cleared by the

QSPI after completing all serial transfers, or when a mode fault occurs.

SPE — QSPI Enable

0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.

1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.

DSCKL[6:0] — Delay before SCK

When the DSCK bit in command RAM is set, this field determines the length of delay from PCS valid to

SCK transition. PCS can be any of the four peripheral chip-select pins. The following equation deter-

mines the actual delay before SCK:

where DSCKL[6:0] equals {1, 2, 3,..., 127}.

When the DSCK value of a queue entry equals zero, then DSCKL[6:0] is not used. Instead, the PCS

valid-to-SCK transition is one-half SCK period.

SPRC1 — QSPI Control Register 1

$YFFC1A

SPE

DSCKL[6:0]

DTL[7:0]

RESET:

SCK Baud Rate

System Clock

SPBR[7:0]

-------------------------------------

SPBR[7:0]

System Clock

SCK

Baud Rate Desired

--------------------------------------------------------------------------

PCS to SCK Delay

DSCKL[6:0]

System Clock

------------------------------------

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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