SPMC68CK338CPV14 datasheet(55/133 Pages) FREESCALE

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MC68CK338

MOTOROLA

MC68CK338TS/D

1. Privileged instruction.

2. Two LPSTOP modes are supported. The first LPSTOP mode is the normal LPSTOP in which the system clock

on the chip is stopped, shutting down all IMB modules with the exception of some parts of the SIML and

CLKOUT. The second LPSTOP mode causes the system clock to be stopped only at the CPU32L, when the

LPSTOP instruction is executed by the CPU32L. As with the normal LPSTOP operation, the CPU32L can be

restarted by an interrupt, a trace, or a reset exception.

Scc

<ea>

If condition true, then destination bits are set to 1;

else, destination bits are cleared to 0

STOP1

#<data>

Data

⇒ SR; STOP

SUB

<ea>, Dn

Dn, <ea>

8, 16, 32

Destination

− Source ⇒ Destination

SUBA

<ea>, An

16, 32

Destination

− Source ⇒ Destination

SUBI

#<data>, <ea>

8, 16, 32

Destination

− Data ⇒ Destination

SUBQ

#<data>, <ea>

8, 16, 32

Destination

− Data ⇒ Destination

SUBX

Dn, Dn

− (An), − (An)

8, 16, 32

Destination

− Source − X ⇒ Destination

SWAP

TAS

<ea>

Destination Tested Condition Codes bit 7 of

Destination

TBLS/TBLU

<ea>, Dn

Dym : Dyn, Dn

8, 16, 32

Dyn

− Dym ⇒ Temp

(Temp

∗ Dn [7 : 0]) ⇒ Temp

(Dym

∗ 256) + Temp ⇒ Dn

TBLSN/TBLUN

<ea>, Dn

Dym : Dyn, Dn

8, 16, 32

Dyn

− Dym ⇒ Temp

(Temp

∗ Dn [7 : 0]) / 256 ⇒ Temp

Dym

+ Temp ⇒ Dn

TRAP

#<data>

none

SSP

− 2 ⇒ SSP; format/vector offset ⇒ (SSP);

SSP

− 4 ⇒ SSP; PC ⇒ (SSP); SR ⇒ (SSP);

vector address

⇒ PC

TRAPcc

none

#<data>

none

16, 32

If cc true, then TRAP exception

TRAPV

none

If V set, then overflow TRAP exception

TST

<ea>

8, 16, 32

Source

− 0, to set condition codes

UNLK

⇒ SP; (SP) ⇒ An, SP + 4 ⇒ SP

Table 33 Instruction Set Summary (Continued)

Instruction

Syntax

Operand Size

Operation

MSW

LSW

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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