SPMC68CK338CPV14 datasheet(48/133 Pages) FREESCALE

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MOTOROLA

MC68CK338

MC68CK338TS/D

4 Low-Power Central Processor Unit

Based on the powerful MC68020, the CPU32L processing module provides enhanced system perfor-

mance and also uses the extensive software base for the Motorola M68000 family.

4.1 Overview

The CPU32L is fully object-code compatible with the M68000 family, which excels at processing calcu-

lation-intensive algorithms and supporting high-level languages. The CPU32L supports all of the

MC68010 and most of the MC68020 enhancements, such as virtual memory support, loop mode oper-

ation, instruction pipeline, and 32-bit mathematical operations. Powerful addressing modes provide

compatibility with existing software programs and increase the efficiency of high-level language compil-

ers. Special instructions, such as table lookup and interpolate and low-power stop, support the specific

requirements of controller applications. Also included is background debug mode, an alternate operat-

ing mode that suspends normal operation and allows the CPU to accept debugging commands from

the development system.

Ease of programming is an important consideration in using a microcontroller. The CPU32L instruction

set is optimized for high performance. The eight 32-bit general-purpose data registers readily support

8-bit (byte), 16-bit (word), and 32-bit (long word) operations. Ease of program checking and diagnosis

is further enhanced by trace and trap capabilities at the instruction level.

Use of high-level languages is increasing as controller applications become more complex and control

programs become larger. High-level languages aid rapid development of software, with less error, and

are readily portable. The CPU32L instruction set supports high-level languages.

4.2 Programming Model

The CPU32L has sixteen 32-bit general registers, a 32-bit program counter, one 32-bit supervisor stack

pointer, a 16-bit status register, two alternate function code registers, and a 32-bit vector base register.

The programming model of the CPU32L consists of a user model shown in Figure 12 and a supervisor

model shown in Figure 13, corresponding to the user and supervisor privilege levels. Some instructions

available at the supervisor level are not available at the user level, allowing the supervisor to protect

system resources from uncontrolled access. Bit S in the status register determines the privilege level.

The user programming model remains unchanged from previous M68000 family microprocessors. Ap-

plication software written to run at the nonprivileged user level migrates without modification to the

CPU32L from any M68000 platform. The move from SR instruction, however, is privileged in the

CPU32L. It is not privileged in the M68000.

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