MAC7200 datasheet(289/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

211

32 byte boundary. If minor loop channel linking is enabled upon channel completion, a configuration error

is reported when the link is attempted if the TCD.citer.e_link bit does not equal the TCD.biter.e_link bit.

All configuration error conditions except scatter/gather and minor loop link error are reported as the

channel is activated and assert an error interrupt request, if enabled. A scatter/gather configuration error is

reported when the scatter/gather operation begins at major loop completion when properly enabled. A

minor loop channel link configuration error is reported when the link operation is serviced at minor loop

completion.

If a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate

bus error flag set. In this case, the state of the channel’s transfer control descriptor is updated by the

dma_engine with the current source address, destination address and current iteration count at the point of

the fault. When a system bus error occurs, the channel is terminated after the read or write transaction

which is already pipelined after errant access, has completed. If a bus error occurs on the last read prior to

beginning the write sequence, the write will execute using the data captured during the bus error. If a bus

error occurs on the last write prior to switching to the next read sequence, the read sequence will execute

before the channel is terminated due to the destination bus error.

The occurrence of any type of error causes the dma_engine to immediately stop, and the appropriate

channel bit in the DMA Error register to be asserted. At the same time, the details of the error condition

are loaded into the DMAES register. The major loop complete indicators, setting the transfer control

descriptor done flag and the possible assertion of an interrupt request, are not affected when an error is

detected. See Figure 12-3 and Table 12-6 for the DMAES definition.

R VLD

00000000000000

Reset

9876543210

CPE

ERRCHN[5:0]

SAE

SOE

DAE

DOE

NCE

SGE

SBE

DBE

Reset

000000000000000

= Unimplemented

Figure 12-3. DMA Error Status (DMAES) Register

Table 12-6. DMAES Field Descriptions

Field

Description

VLD

Logical OR of all DMAERRH and DMAERRL status bits.

0 No DMAERR bits are set.

1 At least one DMAERR bit is set indicating a valid error exists that has not been cleared.

30–15

Reserved, should be cleared.

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