MAC7200 datasheet(285/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

207

write_to_local_memory [channel].daddr = dma_engine.daddr + dma_engine.dlast;

/* restore the major iteration count to the beginning value */

write_to_local_memory [channel].citer = dma_engine.biter;

/* check for interrupt assertion at completion of the major iteration */

if (dma_engine.int_maj)

generate_interrupt (channel);

/* check if the ipd_req is to be disabled at completion of the major iteration */

if (dma_engine.d_req)

DMAERQ [channel] = 0;

/* check for a scatter/gather transfer control descriptor */

if (dma_engine.e_sg) {

/* load new transfer control descriptor from the address defined by dlast_sga */

write_to_local_memory [channel] =

read_from_amba-ahb(dma_engine.dlast_sga,32);

}

if (dma_engine.major.e_link)

TCD[major.linkch].start = 1;

/* specified channel service req */

dma_engine.active = 0;

/* clear the channel busy flag */

dma_engine.done = 1;

/* set the channel done flag */

}

else { /* configuration error detected, abort the channel */

dma_engine.error_status = error_type; /* record the error */

dma_engine.active = 0;

/* clear the channel busy flag */

/* check for interrupt assertion on error */

if (dma_engine.int_err)

generate_interrupt (channel);

}

For more details, consult Section 12.2.4.1, “Register Descriptions.”

12.2.3

External Signal Description

As shown in Figure 12-1, the DMA’s primary platform interfaces are the AMBA-AHB 2.v6 master bus

and the IPS slave bus. The AHB 2.v6 nomenclature refers to the AMBA-AHB 2.0 AHB-Lite protocol,

with AMBA V6 extensions for exclusive access support and extended cache control attributes.

Additionally, the DMA inputs request signals (one per channel) from the peripherals and outputs interrupt

signals (one per channel plus error indicators) to the platform’s interrupt controller. It also interfaces to the

off-platform local memory array. The memory BIST (MBIST) controller is a separate module since test

requirements for the RAM may vary by process technology.

12.2.4

Memory Map/Register Definition

The DMA’s programming model is partitioned into two sections, both mapped into the IPS space: the first

region defines a number of registers providing control functions, while the second region corresponds to

the local transfer control descriptor memory. Reading an unimplemented register bit or memory location

will return the value of zero. Writes to an unimplemented register bit or memory location will be ignored.

Any access to a reserved memory location will result in a bus error.

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