MAC7200 datasheet(8/976 Pages) FREESCALE

8 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

viii

Freescale Semiconductor

6.7

Effects of Reset ..................................................................................................................75

6.7.1

Hardware Configuration ................................................................................................75

6.7.2

Register States................................................................................................................75

6.7.3

Peripheral Disabled State...............................................................................................75

6.7.4

I/O pins ..........................................................................................................................76

6.7.5

Memories .......................................................................................................................76

6.8

System Configuration at Reset ..........................................................................................76

6.9

Resets Differences from MAC71xx...................................................................................77

Chapter 7

Exceptions

7.1

Introduction........................................................................................................................79

7.2

Exception Handling ...........................................................................................................79

7.2.1

Reset...............................................................................................................................80

7.2.2

Undefined Instruction ....................................................................................................80

7.2.3

Software Interrupt ..........................................................................................................80

7.2.4

Prefetch (Instruction) Abort...........................................................................................80

7.2.5

Data Abort......................................................................................................................81

7.2.6

IRQ.................................................................................................................................81

7.2.7

FIQ .................................................................................................................................81

7.3

Interrupts ............................................................................................................................82

7.3.1

Interrupt Clearing...........................................................................................................86

7.3.2

XIRQ and IRQ ...............................................................................................................86

7.3.3

PIT RTI and Timer 4......................................................................................................86

7.3.4

Non-Maskable Interrupt (NMI) .....................................................................................86

7.4

Exceptions Differences from the MAC71xx .....................................................................90

Chapter 8

Debug

8.1

Debug Introduction ............................................................................................................91

8.2

Debug Features ..................................................................................................................91

8.3

Debug Protocol ..................................................................................................................91

8.4

Debug Implementation ......................................................................................................91

8.4.1

JTAG Interface...............................................................................................................91

8.4.1.1

TCK Routing .............................................................................................................93

8.4.1.2

TMS Routing .............................................................................................................93

8.4.1.3

TDI Routing...............................................................................................................93

8.4.1.4

TDO Routing .............................................................................................................94

8.4.2

Synchronization .............................................................................................................95

8.4.3

Debug Reset...................................................................................................................97

8.5

Debug External Pins ..........................................................................................................97

8.6

Debug Bus Aborts..............................................................................................................97

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