MAC7200 datasheet(72/976 Pages) FREESCALE

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Terminology

MAC7200 Microcontroller Family Reference Manual, Rev. 2

lxxii

Freescale Semiconductor

SWT

Software Watchdog Timer

SYSCLK

System clock (fSYS) is the clock used by the core CPU (peripherals operate at fSYS ÷ 2)

Time Quantum

This is equal to the Sclock period. It is the minimum time period used to compose the CAN

protocol bit timing.

Transaction

A bus transaction consists of an address transfer (address phase) and one or more data

transfer(s) (data phase).

Transfer Code

(TCODE)

Message header that identifies the number and/or size of packets to be transferred, and how

to interpret each of the packets.

Transfer Format

The combination of SCK polarity, SCK phase, data MSB/LSB first, and associated CS signal

timing during a serial transmission

Transmit or TX FIFO

First-In-First-Out buffer for transmit data

TUE

Total Unadjusted Error: difference between the expected (ideal) conversion result and the

result delivered by the ATD

UCn

Unified channel n, submodule that performs timed input or output functions supported by the

eMIOS

VCO

Voltage Controlled Oscillator

VREG

Voltage regulator

Watchpoint

A Data or Instruction Breakpoint which does not cause the processor to halt. Instead a pin is

used to signal that the condition occurred. A Watchpoint Message is also generated.

WPTA

Windowed Programmable Time Accumulation

Table ii. Terminology (Continued)

Terms

Description

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