MAC7200 datasheet(5/976 Pages) FREESCALE

5 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

4.2

Signal Properties Summary ..............................................................................................33

4.3

Detailed Signal Descriptions .............................................................................................39

4.3.1

EXTAL, XTAL — Oscillator Pins.................................................................................39

4.3.2

RESET — External Reset Pin .......................................................................................39

4.3.3

XFC — PLL Loop Filter Pin .........................................................................................39

4.3.4

TDI — Test Data In Pin .................................................................................................40

4.3.5

TDO — Test Data Output Pin........................................................................................40

4.3.6

TCK — Test Clock Pin ..................................................................................................40

4.3.7

TMS — Test Mode Pin ..................................................................................................40

4.3.8

PA[0:7] / DATA[0:7] — Port A I/O Pins and external Databus ....................................40

4.3.9

PA[8] / DATA[8] / PCS[4] — Port A I/O Pin, External Databus, and DSPI_B ............40

4.3.10

PA[9] / DATA[9] / PCS[3] / NEX1EVTI — Port A I/O Pin, External Databus,

DSPI_B and Nexus Primary ......................................................................................41

4.3.11

PA[10:15] / DATA[10:15] — Port A I/O Pins and external Databus ............................41

4.3.12

PB[0] / SDA / NEX1MCKO — Port B I/O Pin, IIC and Nexus Primary .....................41

4.3.13

PB[1] / SCL / NEX1EVTO — Port B I/O Pin, IIC and Nexus Primary .......................41

4.3.14

PB[2] / SIN_A / NEX1MSEO — Port B I/O Pin, DSPI_A and Nexus Primary...........41

4.3.15

PB[3] / SOUT_A / NEX1RDY — Port B I/O Pin, DSPI_A and Nexus Primary .........42

4.3.16

PB[4] / SCK_A — Port B I/O Pin and DSPI_A............................................................42

4.3.17

PB[5] / PCS[0] / SS[0] — Port B I/O Pin and DSPI_A ................................................42

4.3.18

PB[6:7] / PCS[1:2] — Port B I/O Pin and DSPI_A ......................................................42

4.3.19

PB[8] / PCS[5] / PCSS — Port B I/O Pin and DSPI_A ................................................42

4.3.20

PB[9] / PCS0 / SS[1] / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary ..43

4.3.21

PB[10] / PCS[5] / PCSS — Port B I/O Pin and DSPI_B ..............................................43

4.3.22

PB[11] / PCS[2] / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary ..........43

4.3.23

PB[12] / PCS[1] — Port B I/O Pin and DSPI_B...........................................................43

4.3.24

PB[13] / SCK_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary .........44

4.3.25

PB[14] / SOUT_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary.......44

4.3.26

PB[15] / SIN_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary...........44

4.3.27

PC[0:2] / ADDR[0:2] — Port C I/O Pins and External address bus .............................44

4.3.28

PC[3] / ADDR[3] / NEX2EVTI — Port C I/O Pins, External Address Bus and Nexus

Secondary ..................................................................................................................44

4.3.29

PC[4] / ADDR[4] / NEX2MCKO — Port C I/O Pins, External Address Bus and

Nexus Secondary .......................................................................................................45

4.3.30

PC[5] / ADDR[5] / NEX2EVTO — Port C I/O Pins, External Address Bus and Nexus

Secondary ..................................................................................................................45

4.3.31

PC[6] / ADDR[6] / NEX2MSEO — Port C I/O Pins, External Address Bus and Nexus

Secondary ..................................................................................................................45

4.3.32

PC[7] / ADDR[7] / NEX2RDY — Port C I/O Pins, External Address Bus and Nexus

Secondary ..................................................................................................................45

4.3.33

PC[8:15] / ADDR[8:15] / MDO[0:7] — Port C I/O Pins, External Address Bus and

Nexus Secondary .......................................................................................................46

4.3.34

PD[0] / BWE[0] / MODB — Port D I/O Pin, External Bus Control & Mode

Selection ....................................................................................................................46

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