MAC7200 datasheet(36/976 Pages) FREESCALE

36 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

xxxvi

Freescale Semiconductor

33.10.2.2

ATD External Trigger Channel Register (ATDETRIGCH).....................................748

33.10.2.3

ATD Prescaler Register (ATDPRE).........................................................................748

33.10.2.4

ATD Operating Modes Register (ATDMODE) .......................................................750

33.10.2.5

ATD Calibration Register (ATDCAL).....................................................................751

33.10.2.6

ATD Predischarge Time Select Register (ATDPTS) ...............................................752

33.10.2.7

ATD Interrupt Register (ATDINT) ..........................................................................753

33.10.2.8

ATD Flag Register (ATDFLAG) .............................................................................754

33.10.2.9

ATD Command Word Register (ATDCW) ..............................................................756

33.10.2.10

ATD Result Register (ATDRR) ...............................................................................761

33.11

Functional Description.....................................................................................................762

33.11.1

General.........................................................................................................................762

33.11.2

Analog Conversion Circuit ..........................................................................................762

33.11.2.1

Analog Input Multiplexer ........................................................................................762

33.11.2.2

Sample Capacitor.....................................................................................................762

33.11.2.3

Reference Voltage Generation .................................................................................762

33.11.2.4

Conversion Circuit...................................................................................................762

33.11.3

Digital Sub-blocks .......................................................................................................763

33.11.3.1

Mode / Timing Control ............................................................................................763

33.11.3.2

Clock Prescaler ........................................................................................................763

33.11.3.3

Bus Interface / Registers ..........................................................................................763

33.11.3.4

Command Word / Result / DMA .............................................................................763

33.11.3.5

SYSTRIG0, SYSTRIG1 / External Trigger Input ...................................................763

33.11.3.6

Flags.........................................................................................................................763

33.11.3.7

Result Adjustment ...................................................................................................764

33.11.3.8

Conversion Control..................................................................................................764

33.11.4

Low Power / Operating Modes....................................................................................764

33.11.5

Conversion Process......................................................................................................765

33.11.5.1

Command Queue .....................................................................................................766

33.11.5.2

Command Processing and DMA Requests..............................................................766

33.11.5.3

Command / Result Timing.......................................................................................769

33.11.6

Conversion Timing ......................................................................................................770

33.11.7

Conversions Using Predischarge .................................................................................772

33.12

Initialization/Application Information .............................................................................774

33.12.1

Initialization .................................................................................................................774

33.12.2

ATD Calibration / Result Adjustment..........................................................................775

33.12.2.1

Gain error.................................................................................................................776

33.12.2.1.1

Gain Error Correction via GCC (Gain Too High) ...............................................776

33.12.2.1.2

Gain Error Correction via OCC (Gain Too High) ...............................................776

33.12.2.1.3

Gain Error Correction via OCC and GCC (Gain Too High) ...............................777

33.12.2.1.4

Gain Error Correction via Warp (Gain Too High)...............................................777

33.12.2.1.5

Gain Error Correction via GCC (Gain Too Low) ................................................778

33.12.2.2

Offset Error ..............................................................................................................778

33.12.2.3

Steps Required For Calibration ...............................................................................779

33.12.2.3.1

Sample Special Channel 75% x (VRH - VRL) ...................................................780

33.12.2.3.2

Sample Special Channel 25% x (VRH - VRL) ...................................................780

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