MAC7200 datasheet(286/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

208

Freescale Semiconductor

Many of the control registers have a bit width that matches the number of channels implemented in the

module, i.e., 16-, 32- or 64-bits in size. Registers associated with a 64-channel design are implemented as

two 32-bit registers, and include an “H” and “L” suffixes, signaling the “high” and “low” portions of the

control function. The descriptions in this section define the 64-channel implementation. For 16- or

32-channel designs, the unused bits are not implemented: reads return zeroes, and writes are ignored.

The DMA module does not include any logic which provides access control. Rather, this function is

supported using the standard access control logic provided by the AIPS controller.

Table 12-4 is a 32-bit view of the DMA’s memory map. Areas not applicable to the MAC72xx family,

which has 16 channels, have been grayed out in theis table.

Table 12-4. DMA 32-bit Memory Map

DMA Offset

0x0000

DMA Control Register (DMACR)

0x0004

DMA Error Status (DMAES)

0x0008

DMA Enable Request High (DMAERQH, Channels 63-32)

0x000c

DMA Enable Request Low (DMAERQL, Channels 31-00)

0x0010

DMA Enable Error Interrupt High (DMAEEIH, Channels 63-32)

0x0014

DMA Enable Error Interrupt Low (DMAEEIL, Channels 31-00)

0x0018

DMA Set Enable

Request

(DMASERQ)

DMA Clear Enable

Request

(DMACERQ)

DMA Set Enable

Error Interrupt

(DMASEEI)

DMA Clear Enable

Error Interrupt

(DMACEEI)

0x001c

DMA Clear Interrupt

Request

(DMACINT)

DMA Clear Error

(DMACERR)

DMA Set Start Bit

(DMASSRT)

DMA Clear Done

Status Bit

(DMACDNE)

0x0020

DMA Interrupt Request High (DMAINTH, Channels 63-32)

0x0024

DMA Interrupt Request Low (DMAINTL, Channels 31-00)

0x0028

DMA Error High (DMAERRH, Channels 63-32)

0x002c

DMA Error Low (DMAERRL, Channels 31-00)

0x0030-0x00fc

Reserved

0x0100

DMA Channel 0

Priority (DCHPRI0)

DMA Channel 1

Priority (DCHPRI1)

DMA Channel 2

Priority (DCHPRI2)

DMA Channel 3

Priority (DCHPRI3)

0x0104

DMA Channel 4

Priority (DCHPRI4)

DMA Channel 5

Priority (DCHPRI5)

DMA Channel 6

Priority (DCHPRI6)

DMA Channel 7

Priority (DCHPRI7)

0x0108

DMA Channel 8

Priority (DCHPRI8)

DMA Channel 9

Priority (DCHPRI9)

DMA Channel 10

Priority (DCHPRI10)

DMA Channel 11

Priority (DCHPRI11)

0x010c

DMA Channel 12

Priority (DCHPRI12)

DMA Channel 13

Priority (DCHPRI13)

DMA Channel 14

Priority (DCHPRI14)

DMA Channel 15

Priority (DCHPRI15)

0x0110

DMA Channel 16

Priority (DCHPRI16)

DMA Channel 17

Priority (DCHPRI17)

DMA Channel 18

Priority (DCHPRI18)

DMA Channel 19

Priority (DCHPRI19)

0x0114

DMA Channel 20

Priority (DCHPRI20)

DMA Channel 21

Priority (DCHPRI21)

DMA Channel 22

Priority (DCHPRI22)

DMA Channel 23

Priority (DCHPRI23)

0x0118

DMA Channel 24

Priority (DCHPRI24)

DMA Channel 25

Priority (DCHPRI25)

DMA Channel 26

Priority (DCHPRI26)

DMA Channel 27

Priority (DCHPRI27)

0x011c

DMA Channel 28

Priority (DCHPRI28)

DMA Channel 29

Priority (DCHPRI29)

DMA Channel 30

Priority (DCHPRI30)

DMA Channel 31

Priority (DCHPRI31)

0x0120

DMA Channel 32

Priority (DCHPRI32)

DMA Channel 33

Priority (DCHPRI33)

DMA Channel 34

Priority (DCHPRI34)

DMA Channel 35

Priority (DCHPRI35)

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