MAC7200 datasheet(293/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

215

12.2.4.1.5

DMA Set Enable Request (DMASERQ)

The DMASERQ register provides a simple memory-mapped mechanism to set a given bit in the

DMAERQ{H,L} registers to enable the DMA request for a given channel. The data value on a register

write causes the corresponding bit in the DMAERQ{H,L} register to be set. A data value of 64 to 127

(regardless of the number of implemented channels) provides a global set function, forcing the entire

contents of DMAERQ{H,L} to be asserted. Reads of this register return all zeroes. See Figure 12-6 and

Table 12-9 for the DMASERQ definition.

12.2.4.1.6

DMA Clear Enable Request (DMACERQ)

The DMACERQ register provides a simple memory-mapped mechanism to clear a given bit in the

DMAERQ{H,L} registers to disable the DMA request for a given channel. The data value on a register

write causes the corresponding bit in the DMAERQ{H,L} register to be cleared. A data value of 64 to 127

(regardless of the number of implemented channels) provides a global clear function, forcing the entire

contents of the DMAERQ{H,L} to be zeroed, disabling all DMA request inputs. Reads of this register

return all zeroes. See Figure 12-7 and Figure 12-10 for the DMACERQ definition.

Table 12-8. DMAEEIH, DMAEEIL Field Descriptions

Field

Description

31–16

Reserved, should be cleared.

15–0

EEIn

n = 0,... 15

Enable Error Interrupt n.

0 The error signal for channel n does not generate an error interrupt.

1 The assertion of the error signal for channel n generate an error interrupt request.

76543210

00000000

SERQ[6:0]

Reset

0000000

= Unimplemented

Figure 12-6. DMA Set Enable Request (DMASERQ) Register

Table 12-9. DMASERQ Field Descriptions

Field

Description

Reserved, should be cleared.

6–0

SERQ[6:0]

Set Enable Request.

0-63

Set the corresponding bit in DMAERQ{H,L}

64-127 Set all bits in DMAERQ{H,L}

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