MAC7200 datasheet(295/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

217

12.2.4.1.8

DMA Clear Enable Error Interrupt (DMACEEI)

The DMACEEI register provides a simple memory-mapped mechanism to clear a given bit in the

DMAEEI{H,L} registers to disable the error interrupt for a given channel. The data value on a register

write causes the corresponding bit in the DMAEEI{H,L} register to be cleared. A data value of 64 to 127

(regardless of the number of implemented channels) provides a global clear function, forcing the entire

contents of the DMAEEI{H,L} to be zeroed, disabling all DMA request inputs. Reads of this register

return all zeroes. See Figure 12-7 and Table 12-12 for the DMACEEI definition.

12.2.4.1.9

DMA Clear Interrupt Request (DMACINT)

The DMACINT register provides a simple memory-mapped mechanism to clear a given bit in the

DMAINT{H,L} registers to disable the interrupt request for a given channel. The given value on a register

write causes the corresponding bit in the DMAINT{H,L} register to be cleared. A data value of 64 to 127

(regardless of the number of implemented channels) provides a global clear function, forcing the entire

contents of the DMAINT{H,L} to be zeroed, disabling all DMA interrupt requests. Reads of this register

return all zeroes. See Figure 12-10 and Table 12-13 for the DMACINT definition.

76543210

00000000

CEEI[6:0]

Reset

0000000

= Unimplemented

Figure 12-9. DMA Clear Enable Error Interrupt (DMACEEI) Register

Table 12-12. DMACEEI Field Descriptions

Field

Description

Reserved, should be cleared.

6–0

CEEI[6:0]

Clear Enable Error Interrupt.

0-63

Clear corresponding bit in DMAEEI{H,L}

64-127 Clear all bits in DMAEEI{H,L}

76543210

00000000

CINT[6:0]

Reset

0000000

= Unimplemented

Figure 12-10. DMA Clear Interrupt Request (DMACINT) Register

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