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MAC7200 bảng dữ liệu(PDF) 255 Page - Freescale Semiconductor, Inc

tên linh kiện MAC7200
Giải thích chi tiết về linh kiện  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 bảng dữ liệu(HTML) 255 Page - Freescale Semiconductor, Inc

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Functional Description
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
177
NOTE
Data Trace is only performed on the ARM7 bus. DMA accesses to the
Advanced High-performance Bus (AHB) are not traced.
11.11.3.2 DTM Message Formats
The A7S Nexus3 block supports five types of DTM Messages: Data Write, Data Read, Data Write
Synchronization, Data Read Synchronization and Error Messages.
11.11.3.2.1
Data Write Messages
The Data Write Message contains the data write value and the address of the write access, relative to the
previous Data Trace Message. Data Write Message information is messaged out in the following format:
11.11.3.2.2
Data Read Messages
The Data Read Message contains the data read value and the address of the read access, relative to the
previous Data Trace Message. Data Read Message information is messaged out in the following format:
11.11.3.2.3
DTM Overflow Error Messages
An Error Message occurs when a new message cannot be queued due to the message queue being full. The
FIFO will discard incoming messages until it has completely emptied the queue. Once emptied, an Error
Message will be queued. The error encoding will indicate which type(s) of messages attempted to be
queued while the FIFO was being emptied.
If only a Data Trace Message attempts to enter the queue while it is being emptied, the Error Message will
incorporate the Data Trace only error encoding (00010). If both OTM and Data Trace Messages attempt
to enter the queue, the Error Message will incorporate the OTM and Data Trace error encoding (00111). If
a Watchpoint also attempts to be queued while the FIFO is being emptied, then the Error Message will
incorporate error encoding (01000).
NOTE
The OVC bits within the DC Register can be set to delay the CPU by
asserting the FIFOFULL signal in order to alleviate (but not eliminate)
potential overruns.
(1–32 bits)
(1–32 bits)
(3 bits)
(4 bits)
(6 bits)
Data Value
Relative Address
Data Size
Src. Proc.
TCODE (000101)
Max length = 77 bits; Min length = 15 bits
Figure 11-39. Data Write Message Format
(1–32 bits)
(1–32 bits)
(3 bits)
(4 bits)
(6 bits)
Data Value
Relative Address
Data Size
Src. Proc.
TCODE (000110)
Max length = 77 bits; Min length = 15 bits
Figure 11-40. Data Read Message Format



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