MAC7200 datasheet(252/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

174

Freescale Semiconductor

•

Setting the TM field of the DC Register to enable Program Trace (DC[2]).

•

Using the PTS field of the WT Register to enable Program Trace on Watchpoint hits (ARM7

watchpoints are configured within the CPU).

NOTE

Setting DC[25] will select the traditional Branch Trace Messaging format

when in Thumb mode. By default, Branch History format is used

(DC[25]=1'b0). Full 32-bit ARM mode always utilizes the Branch History

Message format.

11.11.2.3.2

Addressing

The ARM7 architecture supports a processor mode switch into Thumb mode with the least significant bit

of the address bus set. The A7S Nexus3 module ignores this bit and always treats it as if it is zero (all

instruction addresses are aligned) for the purpose of program trace messaging.

The relative address feature is compliant with the IEEE-ISTO 5001 standard recommendations, and is

designed to reduce the number of bits transmitted for addresses of Indirect Branch Messages.

The address transmitted is relative to the target address of the instruction which triggered the previous

Indirect Branch (or Sync) Message. It is generated by XORing the new address with the previous address,

and then using only the results up to the most significant ‘1’ in the result. To recreate this address, an XOR

of the (most-significant 0-padded) message address with the previously decoded address gives the current

address.

Previous Address (A1) =0x0003FC01, New Address (A2) = 0x0003F365

Figure 11-34. Relative Address Generation and Re-creation

11.11.2.3.3

Branch/Predicate Instruction History (HIST)

In full 32-bit ARM mode (and optionally in Thumb mode), BTM messaging will use the Branch History

format. The branch history (HIST) packet in these messages provides a history of direct branch execution

used for reconstructing the program flow. This packet is implemented as a left-shifting shift register. The

Message Generation:

A1 = 0000 0000 0000 0011 1111 1100 0000 0001

A2 = 0000 0000 0000 0011 1111 0011 0110 0101

⊕ A2 = 0000 0000 0000 0000 0000 1111 0110 0100

Address Message (M1) = 1111 0110 0100

Address Re-creation:

⊕ M1 = A2

A1 = 0000 0000 0000 0011 1111 1100 0000 0001

M1 = 0000 0000 0000 0000 0000 1111 0110 0100

A2 = 0000 0000 0000 0011 1111 0011 0110 0101

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