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MAC7200 bảng dữ liệu(PDF) 253 Page - Freescale Semiconductor, Inc |
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MAC7200 bảng dữ liệu(HTML) 253 Page - Freescale Semiconductor, Inc |
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253 / 976 page ![]() Functional Description MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 175 tools can determine which bit is the end of the history information. The pre-loaded bit itself is not part of the history, but is transmitted with the packet. A value of one (1) is shifted into the history buffer on a taken direct branch (conditional or unconditional) and on any instruction whose predicate condition resolved as true. A value of zero (0) is shifted into the history buffer on any instruction whose predicate condition executed as false as well as on branches not taken. This will include indirect as well as direct branches not taken. 11.11.2.3.4 Sequential Instruction Count (I-CNT) The I-CNT packet, is present in all BTM Messages. For traditional Branch Messages (Thumb mode only), I-CNT represents the number of sequential ARM7 instructions, or non-taken branches in between Direct/Indirect Branch Messages. For Branch History Messages in Thumb mode, I-CNT represents the number of ARM7 instructions executed since the last taken/non-taken direct branch, last taken indirect branch or exception. Not taken indirect branches are considered sequential instructions and cause the instruction count to increment. For Branch History Messages in ARM mode, I-CNT also represents the number of ARM7 instructions executed since the last predicate instruction. The sequential instruction counter overflows when its value reaches 255. The next BTM Message following an instruction counter overflow will be converted to a synchronization type message. NOTE When an undefined instruction causes an exception, the undefined instruction itself will be included in the BTM instruction count. 11.11.2.3.5 Program Trace Queueing A7S Nexus3 implements a programmable depth queue (32 minimum entry recommended) for queuing all messages. Messages that enter the queue are transmitted via the auxiliary pins in the order in which they are queued. 11.11.2.4 Program Trace Timing Diagrams (2 MDO / 1 MSEO configuration) Figure 11-35. Program Trace – Indirect Branch Message (Traditional) 00 01 00 00 00 00 00 00 10 01 01 10 10 TCODE = 4 source processor = 0000 # of sequential instructions = 128 relative address = 8'ha5 00 MCKO MSEO_B MDO[1:0] |
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