MAC7200 datasheet(258/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

180

Freescale Semiconductor

11.11.3.3.3

Relative Addressing

The relative address feature is compliant with the IEEE-ISTO 5001 standard recommendations, and is

designed to reduce the number of bits transmitted for addresses of Data Trace Messages. Refer to

Section 11.11.2.3.2, “Addressing,” for details.

11.11.3.3.4

Data Trace Windowing

Data Write/Read Messages are enabled via the RWT1(2) field in the Data Trace Control Register (DTC)

for each DTM channel. Data Trace windowing is achieved via the address range defined by the DTEA and

DTSA Registers and by the RC1(2) field in the DTC. All ARM7 initiated read/write accesses which fall

inside or outside these address ranges, as programmed, are candidates to be traced.

11.11.3.3.5

ARM7 Bus Cycle Cases

11.11.3.4 Data Trace Timing Diagrams (8 MDO / 2 MSEO configuration)

Figure 11-43. Data Trace – Data Write Message

Figure 11-44. Data Trace – Data Read w/ Sync Message

Table 11-41. ARM7 Bus Cycle Cases

Special Case

Action

ARM7 bus cycle aborted

Cycle ignored

ARM7 bus cycle completed without error

Cycle captured & transmitted

AHB bus cycle initiated by Nexus

Cycle ignored

ARM7 bus cycle is an instruction fetch

Cycle ignored

10101000

00000101

00010100

11101111

TCODE = 5

source processor = 0000

data size = 010 (halfword)

relative address = 8'ha5

write data = 16'hbeef

10111110

MCKO

MSEO_B[1:0]

MDO[7:0]

11000000

00001110

01011001 11010001

TCODE = 14

source processor = 0000

data size = 000 (byte)

full access address = 32'h01468ace

write data = 8'h5c

00101000

00000000

01011100

MCKO

MSEO_B[1:0]

MDO[7:0]

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