TMS320C6720RFP300 datasheet(101/118 Pages) TI

101 / 118 page

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

www.ti.com

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

Table 4-38. RTI Registers (continued)

BYTE ADDRESS

DESCRIPTION

0x4200 0090

RTIDWDCTRL

Digital Watchdog Control. Enables the Digital Watchdog.

0x4200 0094

RTIDWDPRLD

Digital Watchdog Preload. Sets the experation time of the Digital Watchdog.

0x4200 0098

RTIWDSTATUS

Watchdog Status. Reflects the status of Analog and Digital Watchdog.

0x4200 009C

RTIWDKEY

Watchdog Key. Correct written key values discharge the external capacitor.

0x4200 00A0

RTIDWDCNTR

Digital Watchdog Down-Counter

Figure 4-41 shows the bit layout of the CFGRTI register and Table 4-39 contains a description of the bits.

Reserved

CAPSEL1

Reserved

CAPSEL0

R/W, 0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 4-41. CFGRTI Register Bit Layout (0x4000 0014)

Table 4-39. CFGRTI Register Bit Field Description (0x4000 0014)

RESET

READ

BIT NO.

NAME

DESCRIPTION

VALUE

WRITE

31:7,3

Reserved

N/A

Reads are indeterminate. Only 0s should be written to these bits.

6:4

CAPSEL1

R/W

CAPSEL0 selects the input to the RTI Input Capture 0 function.

CAPSEL1 selects the input to the RTI Input Capture 1 function.

2:0

CAPSEL0

R/W

The encoding is the same for both fields:

000 = Select McASP0 Transmit DMA Event

001 = Select McASP0 Receive DMA Event

010 = Select McASP1 Transmit DMA Event

011 = Select McASP1 Receive DMA Event

100 = Select McASP2 Transmit DMA Event

101 = Select McASP2 Receive DMA Event

Other values are reserved and their effect is not determined.

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