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TMS320C6720RFP300 bảng dữ liệu(PDF) 56 Page - Texas Instruments

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4.12 Universal Host-Port Interface (UHPI) [C6727B Only]
4.12.1 UHPI Device-Specific Information
UHPI_HDS[2]
UHPI_HDS[1]
UHPI_HCS
UHPI_HRDY
Internal HSTROBE
Internal HRDY
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008
www.ti.com
The C672x DSP includes a flexible universal host-port interface (UHPI) with more options than the
host-port interface on the C671x DSP.
The UHPI on the C672x DSP supports three major operating modes listed in Table 4-11.
Table 4-11. UHPI Major Modes on C672x
UHPI MAJOR MODE
EXAMPLE FIGURE
Multiplexed Host Address/Data Half-Word (16-Bit) Mode
Figure 4-15
Multiplexed Host Address/Data Fullword (32-Bit) Mode
Figure 4-16
Non-Multiplexed Host Address/Data Fullword (32-Bit) Mode
Figure 4-17
In all modes, the UHPI uses three select inputs (UHPI_HCS, UHPI_HDS[2:1]) which are combined
internally to produce the internal strobe signal HSTROBE. The HSTROBE strobe signal is used in the
UHPI to capture incoming address and control signals on its falling edge and write data on its rising edge.
The UHPI_HCS signal also gates the deassertion of the UHPI_HRDY signal externally.
Figure 4-14. UHPI Strobe and Ready Interaction
The two HPI control pins UHPI_HCNTL[1:0] determine the type of access that the host will perform. Note
that only two of the four access types are supported in Non-Multiplexed Host Address/Data Fullword
Mode.
Table 4-12. HPI Access Types Selected by UHPI_HCNTL[1:0]
NON-
MULTIPLEXED
MULTIPLEXED
UHPI_HCNTL[1:0]
DESCRIPTION
MULTIPLEXED
HALF-WORD
FULLWORD
FULLWORD
00
HPI Control Register (HPIC) Access
Y
Y
Y
01
HPI Data Access (HPID) with autoincrementing address
Y
Y
N
10
HPI Address Register (HPIA) Access
Y
Y
N
11
HPI Data Access (HPID) without autoincrementing
Y
Y
Y
address
CAUTION
When
performing
a
set
of
HPID
with
autoincrementing
address
accesses
(UHPI_HCNTL[1:0] = '01'), the set must begin and end at a word-aligned address. In
addition, all four of the UHPI_HBE[3:0] must be enabled on every access in the set.
CAUTION
The encoding of UHPI_CNTL[1:0] on the C672x DSP is different from HCNTL[1:0] on
the C671x DSP. Modes 01 and 10 are swapped.
Peripheral and Electrical Specifications
56
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