TMS320C6720RFP300 datasheet(57/118 Pages) TI

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TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

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SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

Figure 4-15 illustrates the Multiplexed Host Address/Data Half-Word Mode hookup between the C672x

DSP and an external host microcontroller. In this mode, each 32-bit HPI access is broken up into two

halves. The UHPI_HD[16]/HHWIL pin functions as UHPI_HHWIL which must be '0' during the first half of

access and '1' during the second half.

CAUTION

Unless configured as general-purpose I/O in the UHPI module, UHPI_HD[31:17] and

UHPI_HD[16]/HHWIL will be driven as outputs along with UHPI_HD[15:0] when the HPI

is read, even though only the lower half-word is used to transfer data. This can be

especially problematic for the UHPI_HD[16]/HHWIL pin which should be used as an

input in this mode. Therefore, be sure to configure the upper half of the UHPI_HD bus

as general-purpose I/O pins. Furthermore, be sure to program the UHPI_HD[16]

function as a general-purpose input to avoid a drive conflict with the external host

MCU.

In this mode, as well as the Multiplexed Host Address/Data Fullword mode, the UHPI can be made more

secure by restricting the upper 16 bits of the DSP addresses it can access to what is set in CFGHPIAMSB

and CFGHPIAUMB registers. (See Table 4-15 and Table 4-16).

The host is responsible for configuring the internal HPIA register whether or not it is being overridden by

the device configuration registers CFGHPIAMSB and CFGHPIAUMB.

After the HPIA register has been set, either a single or a group of autoincrementing accesses to HPID

may be performed.

The UHPI_HRDY adds wait states to extend the host MCU access until the C672x DSP has completed

the desired operation.

The HINT signal is available for the DSP to interrupt the host MCU. The UHPI also includes an interrupt to

the DSP core from the host as part of the HPIC register.

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