TMS320C6720RFP300 datasheet(11/118 Pages) TI

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2.5 Program Cache

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

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SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

The C672x DSP executes code directly from a large on-chip 32K-byte program cache. The program cache

has these key features:

• Wide 256-bit path to internal ROM/RAM

• Single-cycle access on cache hits

• 2-cycle miss penalty to internal ROM/RAM

• Caches external memory as well as ROM/RAM

• Direct-mapped

• Modes: Enable, Freeze, Bypass

• Software invalidate to support code overlay

The program cache line size is 256 bits wide and is matched with a 256-bit-wide path between cache and

internal memory. This allows the program cache to fill an entire line (corresponding to eight C67x+ CPU

instructions) with only a single miss penalty of 2 cycles.

The program cache control registers are listed in Table 2-4.

Table 2-4. Program Cache Control Registers

BYTE ADDRESS

DESCRIPTION

L1PISAR

0x2000 0000

L1P Invalidate Start Address

L1PICR

0x2000 0004

L1P Invalidate Control Register

CAUTION

Any application which modifies the contents of program RAM (for example, a program

overlay) must invalidate the addresses from program cache to maintain coherency by

explicitly writing to the L1PISAR and L1PICR registers.

The Cache Mode (Enable, Freeze, Bypass) is configured through a CPU internal register (CSR, bits 7:5).

These options are listed in Table 2-5. Typically, only the Cache Enable Mode is used. But advanced users

may utilize Freeze and Bypass modes to tune performance.

Table 2-5. Cache Modes Set Through PCC Field of CSR CPU Register on C672x

CPU CSR[7:5]

CACHE MODE

000b

Enable (Deprecated - Means direct mapped RAM on some C6000 devices)

010b

Enable - Cache is enabled, cache misses cause a line fill.

011b

Freeze - Cache is enabled, but contents are unchanged by misses.

100b

Bypass - Forces cache misses, cache contents frozen.

Other Values

Reserved - Not Supported

CAUTION

Although the reset value of CSR[7:5] (PCC field) is 000b, the value may be modified

during the boot process by the ROM code. Refer to the appropriate ROM data sheet

for more details. However, note that the cache may be disabled when control is

actually passed to application code. Therefore, it may be necessary to write '010b' to

the PCC field to explicitly enable the cache at the start of application code.

CAUTION

Changing the cache mode through CSR[7:5] does not invalidate any lines already in

the cache. To invalidate the cache after modifications are made to program space, the

control registers L1PISAR and L1PICR must be used.

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