TMS320C6720RFP300 datasheet(70/118 Pages) TI

70 / 118 page

4.13

Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)

Receive Logic

Clock/Frame Generator

State Machine

Clock Check and

Serializer 0

Serializer 1

Serializer y

GIO

Control

DIT RAM

384 C

384 U

Optional

Transmit

Formatter

Receive

Formatter

Transmit Logic

Clock/Frame Generator

State Machine

McASPx (x = 0, 1, 2)

Peripheral

Configuration

Bus

McASP

DMA Bus

(Dedicated)

AHCLKRx

ACLKRx

AFSRx

AMUTEINx

AMUTEx

AFSXx

ACLKXx

AHCLKXx

AXRx[0]

AXRx[1]

AXRx[y]

Pins

Function

Receive Master Clock

Receive Bit Clock

Receive Left/Right Clock or Frame Sync

Transmit Master Clock

Transmit Bit Clock

Transmit Left/Right Clock or Frame Sync

Transmit/Receive Serial Data Pin

Error Detection

The McASPs DO NOT have

dedicated AMUTEINx pins.

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

www.ti.com

The McASP serial port is specifically designed for multichannel audio applications. Its key features are:

• Flexible clock and frame sync generation logic and on-chip dividers

• Up to sixteen transmit or receive data pins and serializers

• Large number of serial data format options, including:

–

TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst).

–

Time slots of 8,12,16, 20, 24, 28, and 32 bits.

–

First bit delay 0, 1, or 2 clocks.

–

MSB or LSB first bit order.

–

Left- or right-aligned data words within time slots

• DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers.

• Extensive error-checking and mute generation logic

• All unused pins GPIO-capable

Figure 4-25. McASP Block Diagram

Peripheral and Electrical Specifications

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