TMS320C6720RFP300 datasheet(42/118 Pages) TI

42 / 118 page

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

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Table 4-2 lists how the synchronization events are associated with event numbers in the dMAX controller.

Table 4-2. dMAX Peripheral Event Input Assignments

EVENT NUMBER

EVENT ACRONYM

EVENT DESCRIPTION

DETR[0]

The CPU triggers the event by creating appropriate transition (edge) on bit0

in DETR register.

DETR[16]

The CPU triggers the event by creating appropriate transition (edge) on bit16

in DETR register.

RTIREQ0

RTI DMA REQ[0]

RTIREQ1

RTI DMA REQ[1]

MCASP0TX

McASP0 TX DMA REQ

MCASP0RX

McASP0 RX DMA REQ

MCASP1TX

McASP1 TX DMA REQ

MCASP1RX

McASP1 RX DMA REQ

MCASP2TX

McASP2 TX DMA REQ

MCASP2RX

McASP2 RX DMA REQ

DETR[1]

The CPU triggers the event by creating appropriate transition (edge) on bit1

in DETR register.

DETR[17]

The CPU triggers the event by creating appropriate transition (edge) on bit17

in DETR register.

UHPIINT

UHPI CPU_INT

SPI0RX

SPI0 DMA_RX_REQ

SPI1RX

SPI1 DMA_RX_REQ

RTIREQ2

RTI DMA REQ[2]

RTIREQ3

RTI DMA REQ[3]

DETR[2]

The CPU triggers the event by creating appropriate transition (edge) on bit2

in DETR register.

DETR[18]

The CPU triggers the event by creating appropriate transition (edge) on bit18

in DETR register.

I2C0XEVT

I2C 0 Transmit Event

I2C0REVT

I2C 0 Receive Event

I2C1XEVT

I2C 1 Transmit Event

I2C1REVT

I2C 1 Receive Event

DETR[3]

The CPU triggers the event by creating appropriate transition (edge) on bit3

in DETR register.

DETR[19]

The CPU triggers the event by creating appropriate transition (edge) on bit19

in DETR register.

Reserved

MCASP0ERR

AMUTEIN0 or McASP0 TX INT or McASP0 RX INT (error on McASP0)

MCASP1ERR

AMUTEIN1 or McASP1 TX INT or McASP1 RX INT (error on McASP1)

MCASP2ERR

AMUTEIN2 or McASP2 TX INT or McASP2 RX INT (error on McASP2)

OVLREQ[0/1]

Error on RTI

DETR[20]

The CPU triggers the event by creating appropriate transition (edge) on bit20

in DETR register.

DETR[21]

The CPU triggers the event by creating appropriate transition (edge) on bit21

in DETR register.

Peripheral and Electrical Specifications

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