TMS320C6720RFP300 datasheet(85/118 Pages) TI

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4.14.3 SPI Electrical Data/Timing

4.14.3.1 Serial Peripheral Interface (SPI) Timing

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

www.ti.com

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

Table 4-27 through Table 4-34 assume testing over recommended operating conditions (see Figure 4-33

through Figure 4-36).

Table 4-27. General Timing Requirements for SPIx Master Modes(1)

NO.

MIN

MAX UNIT

greater of 8P or

tc(SPC)M

Cycle Time, SPIx_CLK, All Master Modes

256P

100 ns

tw(SPCH)M

Pulse Width High, SPIx_CLK, All Master Modes

greater of 4P or 45 ns

tw(SPCL)M

Pulse Width Low, SPIx_CLK, All Master Modes

greater of 4P or 45 ns

Polarity = 0, Phase = 0,

to SPIx_CLK rising

Polarity = 0, Phase = 1,

0.5tc(SPC)M + 2P

Delay, initial data bit valid

to SPIx_CLK rising

td(SIMO_SPC)M

on SPIx_SIMO to initial

Polarity = 1, Phase = 0,

edge on SPIx_CLK(2)

to SPIx_CLK falling

Polarity = 1, Phase = 1,

0.5tc(SPC)M + 2P

to SPIx_CLK falling

Polarity = 0, Phase = 0,

from SPIx_CLK rising

Polarity = 0, Phase = 1,

Delay, subsequent bits

from SPIx_CLK falling

td(SPC_SIMO)M

valid on SPIx_SIMO after

Polarity = 1, Phase = 0,

transmit edge of SPIx_CLK

from SPIx_CLK falling

Polarity = 1, Phase = 1,

from SPIx_CLK rising

Polarity = 0, Phase = 0,

0.5tc(SPC)M – 10

from SPIx_CLK falling

Polarity = 0, Phase = 1,

Output hold time,

0.5tc(SPC)M – 10

from SPIx_CLK rising

SPIx_SIMO valid after

toh(SPC_SIMO)M

receive edge of SPIxCLK,

Polarity = 1, Phase = 0,

0.5tc(SPC)M – 10

except for final bit(3)

from SPIx_CLK rising

Polarity = 1, Phase = 1,

0.5tc(SPC)M – 10

from SPIx_CLK falling

Polarity = 0, Phase = 0,

0.5P + 15

to SPIx_CLK falling

Polarity = 0, Phase = 1,

0.5P + 15

Input Setup Time,

to SPIx_CLK rising

tsu(SOMI_SPC)M

SPIx_SOMI valid before

Polarity = 1, Phase = 0,

receive edge of SPIx_CLK

0.5P + 15

to SPIx_CLK rising

Polarity = 1, Phase = 1,

0.5P + 15

to SPIx_CLK falling

Polarity = 0, Phase = 0,

0.5P + 5

from SPIx_CLK falling

Polarity = 0, Phase = 1,

0.5P + 5

Input Hold Time,

from SPIx_CLK rising

tih(SPC_SOMI)M

SPIx_SOMI valid after

Polarity = 1, Phase = 0,

receive edge of SPIx_CLK

0.5P + 5

from SPIx_CLK rising

Polarity = 1, Phase = 1,

0.5P + 5

from SPIx_CLK falling

(1)

P = SYSCLK2 period

(2)

First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on

SPIx_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPIx_SOMI.

(3)

The final data bit will be held on the SPIx_SIMO pin until the SPIDAT0 or SPIDAT1 register is written with new data.

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