TMS320C6720RFP300 datasheet(60/118 Pages) TI

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EM_D[31:16]/UHPI_HA[15:0]

UHPI_HCNTL[1:0]

UHPI_HD[15:0]

UHPI_HD[16]/HHWIL

UHPI_HD[31:17]

UHPI_HAS(B)

UHPI_HBE[3:0]

UHPI_HRW

UHPI_HDS[2]

UHPI_HDS[1]

UHPI_HCS

UHPI_HRDY

AMUTE2/HINT

A[x:y](A)

D[15:0]

D[16]

BE[3:0](C)

R/W

WE(D)

RD(D)

RDY

INTERRUPT

DSP

External Host MCU

D[31:17]

A[17:2]

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

www.ti.com

Figure 4-17 illustrates the Non-Multiplexed Host Address/Data Fullword mode of the UHPI. In this mode,

the UHPI behaves almost like an asynchronous SRAM except it asserts the UHPI_HRDY signal. This

mode allows the host to randomly access a 64K-byte page in the C672x address space. The upper 32 bits

of the C672x address are set by the DSP (only) through the CFGHPIAMSB and CFGHPIAUMB registers

(see Table 4-15 and Table 4-16).

Two host address lines or host GPIO if address lines are not available.

Not used in this mode.

Byte Enables (active during reads and writes). Some processors support a byte-enable mode on their write enable

pins.

Only required if needed for strobe timing. Not required if CS meets strobe timing requirements.

Figure 4-17. UHPI Non-Multiplexed Host Address/Data Fullword Mode

CAUTION

The EMIF data bus and UHPI HA inputs share the EM_D[31:16]/UHPI_HA[15:0] pins.

When using Non-Multiplexed mode, make sure the EMIF does not drive EM_D[31:16];

otherwise, a drive conflict with the external host MCU may result. Normally, the EMIF

will begin to drive the EM_D[31:16] lines immediately after it completes the SDRAM

initialization sequence, which occurs automatically after RESET is released. To avoid

a drive conflict then, the boot software must set CFGHPI.NMUX to '1' before the EMIF

drives EM_D[31:16]. Setting CFGHPI.NMUX to '1' forces these pins to be input pins.

Peripheral and Electrical Specifications

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