ENC424J600 datasheet(57/168 Pages) MICROCHIP

57 / 168 page

 2010 Microchip Technology Inc.

DS39935C-page 55

ENC424J600/624J600

5.3.2

MODE 2

PSP Mode 2 is also an 8-bit, fully demultiplexed mode

that is available on 64-pin devices only. The parallel

interface consists of 8 bidirectional data pins (AD<7:0>)

and 9 to 15 separate address pins (A<14:0>). To select

PSP Mode 2, tie PSPCFG2 and PSPCFG3 to VSS,

while connecting PSPCFG4 to VDD. Figure 5-4

demonstrates connections required to use Mode 2.

This mode uses a combined Read/Write (R/W) select,

an Enable (EN) strobe pin and a separate Chip Select

pin (CS). These three pins allow the host to select the

device, indicate whether a read or write operation is

desired and signal when valid data is being presented

A logic high signal on the R/W pin indicates that a read

operation is to be performed when the EN strobe is

asserted, while a logic low indicates that a write opera-

tion is to be performed. The state of R/W only affects

the data bus state when the EN signal is active. When

either CS, EN or R/W is driven low, the data bus stays

in a high-impedance state.

To perform a read operation:

Raise the CS line (if connected to the host).

Raise the R/W signal.

Present the address to be read onto the address

bus.

Raise the EN strobe.

Wait the required time for the access to occur.

When EN is raised high, the data bus begins to drive

out indeterminate data for a brief period, then switches

to the correct read data after the appropriate read

access time has elapsed. When the EN strobe is low-

ered, the data bus pins return to a high-impedance

state.

To perform a write operation:

Raise the CS line (if connected to the host).

Lower the R/W signal.

Present the address onto the address bus.

Present the data on the data bus.

Strobe the EN signal high and then low.

Sample timing diagrams for reading and writing data in

this mode are provided in Figure 5-5 and Figure 5-6,

respectively.

FIGURE 5-4:

DEVICE CONNECTIONS FOR PSP MODE 2

Host MCU

ENC624J600

CS(1)

R/W

100 k



A<14:9>(2)

A<8:0>

AD<7:0>

INT/SPISEL

PMCSx

PMRD/PMWR

PMENB

PMA<14:9>

PMA<8:0>

PMD<7:0>

INTx(3)

PSPCFG2

PSPCFG3

PSPCFG4

+3.3V

Note 1:

Use of the CS strobe from the controller is optional. If not used, tie CS to VDD.

Connect these pins when direct addressing of the entire SRAM buffer is required. Tie to VDD when only indirect

addressing is desired.

Use of the external interrupt signal to the controller is optional.

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