ENC424J600 datasheet(53/168 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39935C-page 51

ENC424J600/624J600

5.0

PARALLEL SLAVE PORT

INTERFACE (PSP)

ENC424J600/624J600 devices are designed to

interface directly with the parallel port available on

many microcontrollers, including the Parallel Master

Port (PMP) available on many Microchip PIC® micro-

controllers. The Parallel Slave Port interface is highly

flexible, and can communicate using either Intel® or

Motorola® formats for read and write control strobes. In

the event that a parallel port is not available on the host

microcontroller, a software-managed parallel interface

derived from general purpose I/O pins can be used.

When the PSP interface is enabled, the ENCX24J600

functions as a slave device on the parallel bus. The

host controller must be configured to generate the

destination or target address on the slave device, as

well as the necessary port control signals.

5.1

Physical Implementation

The PSP interface is mutually exclusive with the serial

interface. To enable the PSP and disable the SPI, tie

the INT/SPISEL pin to Vss through an external resistor.

The PSP interface can use from 12 to 34 pins, depend-

ing on the device pin count and the PSP operating

mode. There are up to eight modes, covering the

permutations of data widths, data/address multiplexing

and bus strobe formats. The modes are selected by

tieing each of the PSPCFG<4:0> pins to either VDD or

VSS. The available combinations along with relative

performance metrics are summarized in Table 5-1.

Additional information on physical connections are

provided in Section 2.7.2 “PSP”.

In PSP mode, the CS/CS pin becomes the active-high

Chip Select (CS) pin. A weak internal pull-down is auto-

matically connected to the pin when the PSP interface

is selected, preventing the pin from floating to an

indeterminate state when an external Chip Select

signal is absent.

When CS is in the inactive (logic-low) state, the AD15

(64-pin devices only) and AD<14:0> pins are placed in

a high-impedance state and are 5V tolerant. This

allows the ENCX24J600 to share a single parallel bus

with other slave devices that function the same way

while deselected. All other PSP pins, including the

A<14:0> pins (64-pin devices only) and the port control

strobes, are 5V tolerant inputs at all times. Inputs on

these pins are ignored while the chip select pin is at

logic low.

Unlike the SPI port, the use of chip select is optional

with the PSP. The CS pin can be tied permanently to

VDD if the parallel bus is not shared with other slave

devices. This saves one I/O pin from the host controller

while leaving the ENCX24J600 in a perpetually

selected state.

TABLE 5-1:

OPERATING MODES SUPPORTED BY THE PSP INTERFACE

PSP

Mode

Availability

# Pins(1)

Data

Width

Address/Data

Multiplexing

Control Lines

Theoretical

Performance

@ 10 MHz

(Mbit/s)

44-pin 64-pin

Min

Max

8 bit

CS, RD, WR

8 bit

CS, EN, R/W

16 bit

CS, RD, WRL, WRH

160

16 bit

CS, R/W, B0SEL, B1SEL

160

8 bit

Yes

AL, CS, RD, WR

<80

8 bit

Yes

AL, CS, EN, R/W

<80

16 bit

Yes

AL, CS, RD, WRL, WRH

<80

16 bit

Yes

AL, CS, R/W, B0SEL,

B1SEL

<80

Note 1: Includes only address, data and port control strobes. INT/SPISEL and PSPCFG pins used for mode

configuration are not included.

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