ENC424J600 datasheet(45/168 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39935C-page 43

ENC424J600/624J600

4.5

Three-Byte Instructions

All three-byte instructions are designed to quickly read

or update the Read and Write Pointers used to access

the SRAM buffer area. Unlike the single byte instruc-

tions and RBSEL, each instruction in this group has

distinct read and write implementations.

For read commands (shown in Figure 4-3), the opcode

byte (‘011xxx10’) must be presented on the SI pin,

MSb first, followed by “don’t care” values for the second

and third bytes (9th through 24th SCK rising edges).

Response data is returned on the SO line during the

second and third bytes.

Data on the SO line is also presented in MSb first bit

ordering. However, read commands are intended to

read a 16-bit pointer in little-endian byte ordering.

Therefore, the first byte on the SO line (returned during

SCK clocks, 9 through 16) is the lower byte of the 16-bit

pointer and is followed by the upper byte (returned

during SCK clocks 17 through 24).

Read operations do not affect the ENCX24J600

device’s internal state, and therefore, can be aborted at

any time by deasserting chip select.

For write commands (shown in Figure 4-4), the opcode

byte (‘011xxx00’) must be presented on the SI line,

MSb first, followed immediately by the pointer data to

be written. Like the data returned during a read

operation, the write data must be presented MSb first,

Least Significant Byte first.

If the application only needs to write to the lower byte of

a 16-bit pointer, it can optionally skip the upper byte by

raising chip select after the 16th clock pulse and allowing

adequate chip select hold time to elapse. The hardware

would then update the lower byte of the pointer while

maintaining the original value in the upper byte.

During write operations, the device actively drives the

SO line while the chip select line is active. The value

during this interval is to be ignored.

All three-byte instructions, including read operations,

are considered to be finished at the end of the 24th

SCK clock (if reached). The host controller may issue

another SPI instruction or multiple fixed length

instructions without deasserting chip select.

There are 12 three-byte instructions, which are divided

equally between read and write instructions. They are

listed in Table 4-3.

FIGURE 4-3:

THREE-BYTE READ INSTRUCTION TIMING

FIGURE 4-4:

THREE-BYTE WRITE INSTRUCTION TIMING

SCK

Hi-Z

D7 D6 D5

c4 c3 c2 1

d7 d6 d5 d4 d3 d2 d1 d0

D4 D3 D2 D1 D0

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Opcode

Read Low Byte

Read High Byte

(optional)

SCK

Hi-Z

d5 d4 d3 d2 d1

Hi-Z

c4 c3 c2 0

D7 D6 D5 D4 D3 D2 D1

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Opcode

Write Low Byte

Write High Byte

(optional)

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