PIC18F44J10 datasheet(178/368 Pages) MICROCHIP

178 / 368 page

PIC18F45J10 FAMILY

DS39682E-page 176

16.4.6

MASTER MODE

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPxCON1 and by setting

the SSPEN bit. In Master mode, the SCLx and SDAx

lines are manipulated by the MSSP hardware.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop

conditions. The Stop (P) and Start (S) bits are cleared

from a Reset or when the MSSP module is disabled.

Control of the I2C bus may be taken when the P bit is

set, or the bus is Idle, with both the S and P bits clear.

In Firmware Controlled Master mode, user code

conducts all I2C bus operations based on Start and

Stop bit conditions.

Once Master mode is enabled, the user has six

options.

Assert a Start condition on SDAx and SCLx.

Assert a Repeated Start condition on SDAx and

SCLx.

Write to the SSPxBUF register initiating

transmission of data/address.

Configure the I2C port to receive data.

Generate an Acknowledge condition at the end

of a received byte of data.

Generate a Stop condition on SDAx and SCLx.

The following events will cause the MSSP Interrupt

Flag bit, SSPxIF, to be set (and MSSP interrupt, if

enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

• Acknowledge transmit

• Repeated Start

FIGURE 16-16:

MSSP BLOCK DIAGRAM (I

2C™ MASTER MODE)

Note:

The MSSP module, when configured in

I2C Master mode, does not allow queueing

of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPxBUF register to

initiate transmission before the Start con-

dition is complete. In this case, the

SSPxBUF will not be written to and the

WCOL bit will be set, indicating that a write

to the SSPxBUF did not occur.

Read

Write

SSPxSR

Start bit, Stop bit,

SSPxBUF

Internal

Data Bus

Set/Reset S, P, WCOL (SSPxSTAT, SSPxCON1);

Shift

Clock

MSb

LSb

SDAx

Acknowledge

Generate

Stop bit Detect,

Write Collision Detect,

Clock Arbitration,

State Counter for

End of XMIT/RCV

SCLx

SCLx In

Bus Collision

SDAx In

SSPxADD<6:0>

Baud

Set SSPxIF, BCLxIF;

Reset ACKSTAT, PEN (SSPxCON2)

Rate

Generator

SSPM<3:0>

Start bit Detect,

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