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PIC18F44J10 bảng dữ liệu(PDF) 93 Page - Microchip Technology

tên linh kiện PIC18F44J10
Giải thích chi tiết về linh kiện  28/40/44-Pin High-Performance, RISC Microcontrollers
PDF  368 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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PIC18F44J10 bảng dữ liệu(HTML) 93 Page - Microchip Technology

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© 2009 Microchip Technology Inc.
DS39682E-page 91
PIC18F45J10 FAMILY
REGISTER 9-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
R/W-0
U-0
U-0
R/W-0
U-0
U-0
R/W-0
OSCFIE
CMIE
—
—BCL1IE
—
—
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OSCFIE:
Oscillator Fail Interrupt Enable bit
1
= Enabled
0
= Disabled
bit 6
CMIE:
Comparator Interrupt Enable bit
1
= Enabled
0
= Disabled
bit 5-4
Unimplemented:
Read as ‘0’
bit 3
BCL1IE:
Bus Collision Interrupt Enable bit (MSSP1 module)
1
= Enabled
0
= Disabled
bit 2-1
Unimplemented:
Read as ‘0’
bit 0
CCP2IE:
CCP2 Interrupt Enable bit
1
= Enabled
0
= Disabled
REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
SSP2IE
BCL2IE
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SSP2IE:
Master Synchronous Serial Port 2 Interrupt Enable bit
1
= Enabled
0
= Disabled
bit 6
BCL2IE:
Bus Collision Interrupt Enable bit (MSSP2 module)
1
= Enabled
0
= Disabled
bit 5-0
Unimplemented:
Read as ‘0’



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