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PIC18F44J10 bảng dữ liệu(PDF) 25 Page - Microchip Technology

tên linh kiện PIC18F44J10
Giải thích chi tiết về linh kiện  28/40/44-Pin High-Performance, RISC Microcontrollers
PDF  368 Pages
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PIC18F44J10 bảng dữ liệu(HTML) 25 Page - Microchip Technology

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© 2009 Microchip Technology Inc.
DS39682E-page 23
PIC18F45J10 FAMILY
2.0
GUIDELINES FOR GETTING
STARTED WITH PIC18FJ
MICROCONTROLLERS
2.1
Basic Connection Requirements
Getting started with the PIC18F45J10 family family of
8-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
The following pins must always be connected:
•All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
•All AVDD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
•MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
• ENVREG (if implemented) and VCAP/VDDCORE pins
(see Section 2.4 “Voltage Regulator Pins
(VCAP/VDDCORE)”
)
These pins must also be connected if they are being
used in the end application:
• PGC/PGD pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
•VREF+/VREF- pins used when external voltage
reference for analog modules is implemented
The minimum mandatory connections are shown in
Figure 2-1.
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
Note:
The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
PIC18FXXJXX
VDD
VSS
VSS
VDD
C1
R1
VDD
MCLR
VCAP/VDDCORE
R2
ENVREG
(1)
C7
C2(2)
C3(2)
C4(2)
C5(2)
C6(2)
Key (all values are recommendations):
C1 through C6: 0.1
μF, 20V ceramic
C7: 10
μF, 6.3V or greater, tantalum or ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
Note
1:
See Section 2.4 “Voltage Regulator Pins
(VCAP/VDDCORE)”
for explanation of
ENVREG pin connections.
2:
The example shown is for a PIC18FJ device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
(1)



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