PIC18F44J10 datasheet(65/368 Pages) MICROCHIP

65 / 368 page

DS39682E-page 63

PIC18F45J10 FAMILY

TMR0H

Timer0 Register High Byte

0000 0000

48, 117

TMR0L

Timer0 Register Low Byte

xxxx xxxx

48, 117

T0CON

TMR0ON

T08BIT

T0CS

T0SE

PSA

T0PS2

T0PS1

T0PS0

1111 1111

48, 115

OSCCON

IDLEN

—

—OSTS

—

SCS1

SCS0

0--- q-00

32, 48

WDTCON

—

—SWDTEN

--- ---0

48, 242

RCON

IPEN

—CM

POR

BOR(1)

0-11 11q0

42, 46, 94

TMR1H

Timer1 Register High Byte

xxxx xxxx

48, 124

TMR1L

Timer1 Register Low Byte

xxxx xxxx

48, 124

T1CON

RD16

T1RUN

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

0000 0000

48, 119

TMR2

Timer2 Register

0000 0000

48, 126

PR2

Timer2 Period Register

1111 1111

48, 126

T2CON

—

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0

TMR2ON

T2CKPS1

T2CKPS0

-000 0000

48, 125

SSP1BUF

MSSP1 Receive Buffer/Transmit Register

xxxx xxxx

48, 158

SSP1ADD

MSSP1 Address Register in I2C™ Slave mode. MSSP1 Baud Rate Reload Register in I2C Master mode.

0000 0000

48, 159

SSP1STAT

SMP

CKE

D/A

R/W

0000 0000

48, 150,

160

SSP1CON1

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000 0000

48, 151,

161

SSP1CON2

GCEN

ACKSTAT

ACKDT

ACKEN

RCEN

PEN

RSEN

SEN

0000 0000

48, 162

GCEN

ACKSTAT

ADMSK5(3)

ADMSK4(3) ADMSK3(3)

ADMSK2(3)

ADMSK1(3)

SEN

0000 0000

48, 163

ADRESH

A/D Result Register High Byte

xxxx xxxx

48, 223

ADRESL

A/D Result Register Low Byte

xxxx xxxx

48, 223

ADCON0

ADCAL

—

CHS3

CHS2

CHS1

CHS0

GO/DONE

ADON

0-00 0000

48, 218

ADCON1

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

--00 0qqq

48, 218

ADCON2

ADFM

—

ACQT2

ACQT1

ACQT0

ADCS2

ADCS1

ADCS0

0-00 0000

48, 218

CCPR1H

Capture/Compare/PWM Register 1 High Byte

xxxx xxxx

49, 128

CCPR1L

Capture/Compare/PWM Register 1 Low Byte

xxxx xxxx

49, 128

CCP1CON

P1M1(2)

P1M0(2)

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M0

0000 0000

49, 128,

CCPR2H

Capture/Compare/PWM Register 2 High Byte

xxxx xxxx

49, 128

CCPR2L

Capture/Compare/PWM Register 2 Low Byte

xxxx xxxx

49, 128

CCP2CON

—

DC2B1

DC2B0

CCP2M3

CCP2M2

CCP2M1

CCP2M0

--00 0000

49, 128

BAUDCON

ABDOVF

RCIDL

—SCKP

BRG16

—

WUE

ABDEN

01-0 0-00

49, 196

ECCP1DEL

PRSEN

PDC6(2)

PDC5(2)

PDC4(2)

PDC3(2)

PDC2(2)

PDC1(2)

PDC0(2)

0000 0000

49, 144

ECCP1AS

ECCPASE

ECCPAS2

ECCPAS1

ECCPAS0

PSSAC1

PSSAC0

PSSBD1(2)

PSSBD0(2) 0000 0000

49, 146

CVRCON

CVREN

CVROE

CVRR

CVRSS

CVR3

CVR2

CVR1

CVR0

0000 0000

49, 232

CMCON

C2OUT

C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0

0000 0111

49, 226

TABLE 6-3:

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Details

on page:

Legend:

= unknown, u = unchanged, - = unimplemented, q = value depends on condition

Note

See Section 5.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”.

These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as ‘-’.

Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 16.4.3.2 “Address

Masking”

for details.

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