PIC18F44J10 datasheet(46/368 Pages) MICROCHIP

46 / 368 page

PIC18F45J10 FAMILY

DS39682E-page 44

5.5

Configuration Mismatch (CM)

The Configuration Mismatch (CM) Reset is designed to

detect and attempt to recover from random, memory

corrupting events. These include Electrostatic Discharge

(ESD) events, which can cause widespread, single-bit

changes throughout the device and result in catastrophic

failure.

In PIC18FXXJ Flash devices, the device Configuration

registers (located in the configuration memory space)

are continuously monitored during operation by

comparing their values to complimentary shadow reg-

isters. If a mismatch is detected between the two sets

of registers, a CM Reset automatically occurs. These

events are captured by the CM bit (RCON<5>). The

state of the bit is set to ‘0’ whenever a CM event occurs;

it does not change for any other Reset event.

A CM Reset behaves similarly to a Master Clear Reset,

RESET

instruction, WDT time-out or Stack Event

Resets. As with all hard and power Reset events, the

device Configuration Words are reloaded from the

Flash Configuration Words in program memory as the

device restarts.

5.6

Power-up Timer (PWRT)

PIC18F45J10 family devices incorporate an on-chip

Power-up Timer (PWRT) to help regulate the Power-on

Reset process. The PWRT is always enabled. The

main function is to ensure that the device voltage is

stable before code is executed.

The Power-up Timer (PWRT) of the PIC18F45J10

family devices is an 11-bit counter which uses the

INTRC source as the clock input. This yields an

approximate time interval of 2048 x 32

μs= 65.6 ms.

While the PWRT is counting, the device is held in

Reset.

The power-up time delay depends on the INTRC clock

and will vary from chip to chip due to temperature and

process variation. See DC parameter 33 for details.

5.6.1

TIME-OUT SEQUENCE

If enabled, the PWRT time-out is invoked after the POR

pulse has cleared. The total time-out will vary based on

the status of the PWRT. Figure 5-3, Figure 5-4,

Figure 5-5

and

Figure 5-6

all

depict

time-out

sequences on power-up with the Power-up Timer

enabled.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the PWRT will expire. Bringing

MCLR

high

will

begin

execution

immediately

(Figure 5-5). This is useful for testing purposes, or to

synchronize more than one PIC18F device operating in

parallel.

FIGURE 5-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

TPWRT

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

INTERNAL RESET

PIC18F44J10 bảng dữ liệu(PDF) 46 Page - Microchip Technology

PIC18F44J10 bảng dữ liệu(HTML) 46 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL