CoreMP7

v2.6

3

General Description

The CoreMP7 processor architecture, core, and functional diagrams are illustrated in the following figures:

•

The CoreMP7 block diagram is shown in Figure 1.

•

The CoreMP7 core is shown in Figure 2 on page 4.

•

The CoreMP7 functional diagram is shown in Figure 3 on page 5.

Figure 1 •

CoreMP7 Top-Level Block Diagram

DBGTMS

DBGnTRST

DBGTDI

DBGTDO

DBGRNG(0)

DBGRNG(1)

DBGEXT(0)

DBGEXT(1)

WDATA[31:0]

RDATA[31:0]

CPU

DBGTCKEN

LOCK

WRITE

SIZE[1:0]

PROT[1:0]

TRANS[1:0]

ADDR[31:0]

Coprocessor

Interface Signals

EmbeddedICE-RT

Macrocell

EmbeddedICE-RT

TAP Controller