công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

ARMV4T bảng dữ liệu(PDF) 24 Page - Actel Corporation

tên linh kiện ARMV4T
Giải thích chi tiết về linh kiện  CoreMP7
PDF  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  ACTEL [Actel Corporation]
Trang chủ  http://www.actel.com
Logo ACTEL - Actel Corporation

ARMV4T bảng dữ liệu(HTML) 24 Page - Actel Corporation

Back Button ARMV4T Datasheet HTML 20Page - Actel Corporation ARMV4T Datasheet HTML 21Page - Actel Corporation ARMV4T Datasheet HTML 22Page - Actel Corporation ARMV4T Datasheet HTML 23Page - Actel Corporation ARMV4T Datasheet HTML 24Page - Actel Corporation ARMV4T Datasheet HTML 25Page - Actel Corporation ARMV4T Datasheet HTML 26Page - Actel Corporation ARMV4T Datasheet HTML 27Page - Actel Corporation ARMV4T Datasheet HTML 28Page - Actel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 24 / 30 page
background image
CoreMP7
24
v2.6
•
A separate UART to communicate with the
monitor program is not required.
The debugging of the target system requires the
following:
•
A PC host computer running Windows to run the
debugger software
•
An EmbeddedICE Protocol Converter, a separate
box which converts the serial interface to signals
compatible with the JTAG interface and a target
system with a JTAG interface and an ARM Debug
Architecture compliant core.
Once the system is connected, the debugger can start
communicating with the target system via the RVI-ME
(which is an EmbeddedICE Interface Converter).
The debug extensions consist of several scan chains
around the processor core, and some additional signals
that are used to control the behavior of the core for
debug purposes. The most significant of these additional
signals are as follows:
BREAKPT: This core signal enables external hardware to
halt processor execution for debug purposes. When
HIGH during an instruction fetch, the instruction is
tagged as breakpointed, and the core stops if this
instruction reaches execute.
DBGRQ: This core signal is a level-sensitive input that
causes the CPU core to enter debug state when the
current instruction has completed.
DBGACK: This core signal is an output from the CPU
core that goes HIGH when the core is in debug state so
that external devices can determine the current state of
the core.
RealView ICE uses these, and other signals, through the
debug interface of the processor core, for example by
writing to the control register of the EmbeddedICE logic.
For more details, refer to the debug interface section of
the ARM datasheet or technical reference manual for
your core.
JTAG Debug Interface
The RVI-ME ICE run control unit is supplied with a short
ribbon cable. These both terminate in a 20-way 2.54 mm
pitch IDC connector. You can use the cable to mate with
a keyed box header on the target. The pinout is shown in
Figure 16.
Figure 16 •
JTAG Interface Pinout
Vsupply
GND
GND
GND
GND
GND
GND
GND
GND
GND
VTref
nTRST
TDI
TMS
TCK
RTCK
TDO
nSRST
DBGRQ
DBGACK
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com