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ARMV4T bảng dữ liệu(PDF) 24 Page - Actel Corporation |
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ARMV4T bảng dữ liệu(HTML) 24 Page - Actel Corporation |
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24 / 30 page ![]() CoreMP7 24 v2.6 • A separate UART to communicate with the monitor program is not required. The debugging of the target system requires the following: • A PC host computer running Windows to run the debugger software • An EmbeddedICE Protocol Converter, a separate box which converts the serial interface to signals compatible with the JTAG interface and a target system with a JTAG interface and an ARM Debug Architecture compliant core. Once the system is connected, the debugger can start communicating with the target system via the RVI-ME (which is an EmbeddedICE Interface Converter). The debug extensions consist of several scan chains around the processor core, and some additional signals that are used to control the behavior of the core for debug purposes. The most significant of these additional signals are as follows: BREAKPT: This core signal enables external hardware to halt processor execution for debug purposes. When HIGH during an instruction fetch, the instruction is tagged as breakpointed, and the core stops if this instruction reaches execute. DBGRQ: This core signal is a level-sensitive input that causes the CPU core to enter debug state when the current instruction has completed. DBGACK: This core signal is an output from the CPU core that goes HIGH when the core is in debug state so that external devices can determine the current state of the core. RealView ICE uses these, and other signals, through the debug interface of the processor core, for example by writing to the control register of the EmbeddedICE logic. For more details, refer to the debug interface section of the ARM datasheet or technical reference manual for your core. JTAG Debug Interface The RVI-ME ICE run control unit is supplied with a short ribbon cable. These both terminate in a 20-way 2.54 mm pitch IDC connector. You can use the cable to mate with a keyed box header on the target. The pinout is shown in Figure 16. Figure 16 • JTAG Interface Pinout Vsupply GND GND GND GND GND GND GND GND GND VTref nTRST TDI TMS TCK RTCK TDO nSRST DBGRQ DBGACK 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 |
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