CoreMP7

22

v2.6

AC Timing Parameter Definitions

Table 6 shows target AC parameters. All figures are expressed as percentages of the CLK period at maximum

operating frequency.

Note: Where 0% is shown, this indicates the hold time to clock edge plus the maximum clock skew for internal clock

buffering.

Table 6 •

AC Timing Parameters

Symbol

Parameter

Min

Max

CLK cycle time

100%

–

CLKEN input setup to rising CLK

60%

–

CLKEN input hold from rising CLK

–

ABORT input setup to rising CLK

40%

–

ABORT input hold from rising CLK

–0%

RDATA input setup to rising CLK

10%

–

nRESET input setup to rising CLK

90%

–

DBGnTRST input setup to rising CLK

25%

RDATA input hold from rising CLK

–

Rising CLK to CPTBIT valid

–

90%

Rising CLK to DBGnEXEC, DBGINSTRVALID valid

–

40%

Rising CLK to DMORE, LOCK valid

–

90%

Rising CLK to ADDR valid

–

90%

ADDR hold time from rising CLK

>0%

–

Rising CLK to control valid

–

90%

Control hold time from rising CLK

>0%

–

Rising CLK to transaction type valid

–

50%

Transaction type hold time from rising CLK

>0%

–

Rising CLK to WDATA valid

–

40%

WDATA hold time from rising CLK

>0%

–

CPA, CPB input setup to rising CLK

20%

–

CPA, CPB input hold from rising CLK

–0%

Rising CLK to coprocessor control valid

–

80%

Coprocessor control hold time from rising CLK

>0%

–

Rising CLK to coprocessor CPnI valid

–

40%

Coprocessor CPnI hold time from rising CLK

>0%

–

nFIQ, nIRQ, input setup to rising CLK

10%

–

Notes: