CoreMP7

26

v2.6

The EmbeddedICE logic which implements the on-chip

debug function in the CoreMP7 debug architecture is

described in detail in the ARM7TDMI-S (rev 4) Technical

Reference Manual (ARM DDI0234A), published by ARM

Limited, and is available via Internet at www.arm.com.

The CoreMP7 debug architecture uses a JTAG port as a

method of accessing the core. The debug architecture

uses EmbeddedICE logic which resides on chip with the

CoreMP7 core. The EmbeddedICE has its own scan chain

that is used to insert watchpoints and breakpoints for

the CoreMP7. The EmbeddedICE logic consists of two

real-time watchpoint registers, together with a control

and status register. One or both of the watchpoint

registers can be programmed to halt the CoreMP7 core.

Execution is halted when a match occurs between the

values programmed into the EmbeddedICE logic and the

values currently appearing on the address bus, databus,

and some control signals. Any bit can be masked so that

its value does not affect the comparison. Either

watchpoint register can be configured as a watchpoint

(i.e., on a data access) or a break point (i.e., on an

instruction fetch). The watchpoints and breakpoints can

be combined such that:

•

The conditions on both watchpoints must be

satisfied before the CoreMP7 is stopped. The

CHAIN functionality requires two consecutive

conditions to be satisfied before the core is halted.

An example of this would be to set the first

breakpoint to trigger on an access to a peripheral

and the second to trigger on the code segment

that performs the task switching. Therefore the

breakpoints trigger the information regarding

which task has switched out that will be ready for

examination.

•

The watchpoints can be configured such that a

range

of

addresses

are

enabled

for

the

watchpoints to be active. The RANGE function

allows the breakpoints to be combined such that a

breakpoint is to occur if an access occurs in the

bottom 256 bytes of memory but not in the

bottom 32 bytes.

The CoreMP7 core has a Debug Communication Channel

function in-built. The debug communication channel

allows a program running on the target to communicate

with the host debugger or another separate host

without stopping the program flow or even entering the

debug state. The debug communication channel is

accessed as coprocessor 14 by the program running on

the CoreMP7 core. The debug communication channel

allows the JTAG port to be used for sending and

receiving data without affecting the normal program

flow. The debug communication channel data and

control registers are mapped in to addresses in the

EmbeddedICE logic.

Table 8 •

Debug Communication Channel Signals

Signal Name

Type

Description

TMS

Input

Test Mode Select. The TMS pin selects the next state in the TAP state machine.

TCK

Input

Test Clock. This allows shifting of the data in, on the TMS and TDI pins. It is a positive edge triggered

clock with the TMS and TCK signals that define the internal state of the device.

TDI

Input

Test Data In. This is the serial data input for the shift register.

TDO

Output

Test Data Output. This is the serial data output from the shift register. Data is shifted out of the device

on the negative edge of the TCK signal.

nTRST

Input

Test Reset.The nTRST pin can be used to reset the test logic within the EmbeddedICE logic.

RTCK

Output

Returned Test Clock. Extra signal added to the JTAG port. Required for designs based on COREMP7

processor core. Multi-ICE (development system from ARM) uses this signal to maintain synchronization

with targets having slow or widely varying clock frequency. For details, refer to the Multi-ICE System