ARMV4T datasheet(18/30 Pages) ACTEL

18 / 30 page

CoreMP7

v2.6

Timing Shell

The BFM incorporates a timing shell, which performs

setup/hold checks on inputs and delays outputs by the

appropriate amount from the rising clock edge.

Example BFM Use Case

This provides an example use case of the ARM7 BFM. The

example SoC used in this section is the same as that

shown in Figure 9 on page 15. In this system, the

developer requires two Actel IP cores: the MAC 10/100

and the CoreUART.

SPIRIT Attributes

CoreConsole has access to a database of Actel IP cores

and a list of attributes for each core. These attributes are

organized according to the SPIRIT specification, in XML.

For example, in the case of the CoreUART, the attributes

would indicate that there are three registers, as in

Table 4.

Based on these attributes, CoreConsole can determine

that when generating the BFM script, there are three

locations corresponding to the UART that can be

accessed. In this case, none of the registers are RW, so

there will not be any self-checking that can be

performed

for

the

UART.

Nevertheless,

the

bus

transactions do take place and the cycles may be viewed

in a waveform of the simulator.

Memory Map

The designer must feed in the memory map of the SoC to

CoreConsole. During this stage, the absolute address

ranges of the various system resources in the ARM7

memory map are fed in. Also, user-friendly instance

names of these resources are fed in.

For example, the user could feed the memory map

information into CoreConsole that is given in Table 5.

Based on the information in Table 5, CoreConsole

generates the SoC subsystem corresponding to the Actel

IP cores present. It also generates a BFM script, which

accesses all the registers in the Actel IP cores.

Processor Choice

In this example, the user selects an ARM7 as the

processor of choice in CoreConsole. The BFM in this

specification only relates to ARM7.

Bus Fabric Selection

The user may select one of a number of bus fabrics in

CoreConsole. For example, the user could select AMBA

AHB-Lite. However, this selection is irrelevant for the

ARM7 BFM, as it is concerned only with generating

native ARM7 bus based transactions.

Automatic BFM Scriptlet

At this point, having run CoreConsole to completion, a

BFM scriptlet is available. This would look something like

the following:

read B uart 0;

write B uart 4 bb;

read B uart 8;

write B mac 30 11;

readcheck B mac 11;

Run BFM

The developer can run the BFM with the automatic script

or edit the script to put in bus transactions to/from any

new logic that has been added to the SoC. For example,

transactions to/from the registers in the new VideoCodec

block could be added.

The skeleton system-level testbench, generated by

CoreConsole, could also be modified, to add some

external resources (e.g., models of SSRAM and Flash) and

some high-level tasks.

Upon running the system simulation, messages appear in

the console window of the simulation tool.

Table 4 •

CoreUART Attributes

Offset

Read/Write

Width

Uart Status Register

Byte

Uart Tx data

Byte

Uart Rx data

Byte

Table 5 •

Memory Map Information

Resource

Actel IP Core

Address Range

ssram

0-3fffff

flash

400000-7fffff

uart

c00000-c0000b

mac

d00000-d00040

videocodec

e00000-e000ff

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