ARMV4T datasheet(7/30 Pages) ACTEL

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CoreMP7

v2.6

Programmer’s Model

This section summarizes the programmer’s model of the

CoreMP7. Supporting detail is available in the ARM

ARM7TDMI-S Technical Reference Manual (available for

download at www.arm.com) and the ARM Architecture

Reference

Manual,

which

can

purchased

www.amazon.com.

The

CoreMP7

processor

implements

the

ARMv4T

architecture

and

includes

both

the

32-bit

ARM

instruction set and the 16-bit Thumb instruction set.

Processor Operating States

The CoreMP7 processor has two operating states:

ARM state:

32-bit, word-aligned ARM instructions are

executed in this state.

Thumb state: 16-bit, halfword-aligned Thumb instructions

are executed in this state.

In Thumb state, the Program Counter (PC) uses bit 1 to

select between alternate halfwords.

Note: Transition between ARM and Thumb states does

not affect the processor mode or the register contents.

Switching State

You can switch the operating state of the CoreMP7

between ARM state and Thumb state using the BX

instruction.

This

described

fully

the

ARM

Architecture Reference Manual.

All exception handling is performed in ARM state. If an

exception occurs in Thumb state, the processor reverts to

ARM state. The transition back to Thumb state occurs

automatically on return.

Memory Formats

The CoreMP7 processor views memory as a linear

collection of bytes, numbered in ascending order from

zero:

•

Bytes 0 to 3 hold the first stored word.

•

Bytes 4 to 7 hold the second stored word.

•

Bytes 8 to 11 hold the third stored word.

Although both Little Endian and Big Endian memory

formats are supported, it is recommended that you use

Little Endian format.

Data Types

The CoreMP7 processor supports the following data

types:

•

Word (32-bit)

•

Halfword (16-bit)

•

Byte (8-bit)

You must align these as follows:

•

Word quantities must be aligned to four-byte

boundaries.

•

Halfword quantities must be aligned to two-byte

boundaries.

•

Byte quantities can be placed on any byte

boundary.

Operating Modes

The CoreMP7 processor has seven operating modes:

•

User mode is the usual ARM program execution

state, and is used for executing most application

programs.

•

Fast interrupt (FIQ) mode supports a data transfer

or channel process.

•

Interrupt (IRQ) mode is used for general-purpose

interrupt handling.

•

Supervisor mode is a protected mode for the

operating system.

•

Abort mode is entered after a data or instruction

prefetch abort.

•

System mode is a privileged user mode for the

operating system.

•

Undefined mode is entered when an undefined

instruction is executed.

Modes other than User mode are collectively known as

privileged modes. Privileged modes are used to service

interrupts or exceptions, or to access protected resources.

Registers

The CoreMP7 processor has a total of 37 registers:

•

31 general-purpose 32-bit registers

•

6 status registers

These registers are not all accessible at the same time.

The processor state and operating mode determine

which registers are available to the programmer.

The ARM State Register Set

In ARM state, 16 general registers and one or two status

registers are accessible at any one time. In privileged

modes, mode-specific banked registers become available.

Figure 4 on page 8 shows which registers are available in

each mode.

The ARM state register set contains 16 directly accessible

registers, r0 to r15. An additional register, the Current

Program Status Register (CPSR), contains condition code

flags, and the current mode bits. Registers r0 to r13 are

general-purpose registers used to hold either data or

address values. Registers r14 and r15 have special

functions as the Link Register and Program Counter.

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