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3819 bảng dữ liệu(PDF) 162 Page - Renesas Technology Corp |
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3819 bảng dữ liệu(HTML) 162 Page - Renesas Technology Corp |
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162 / 218 page ![]() 148 2. APPLICATION MITSUBISHI MICROCOMPUTER 3819 Group 2.7 Zero cross detection circuit 3819 Group USER’S MANUAL Fig. 2.7.3 Structure of Interrupt request register 1 Fig. 2.7.4 Structure of Interrupt control register 1 Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At reset RW 0 1 2 3 0 0 0 0 Interrupt request reigster 1 (IREQ1) [Address:3C16] Name INT0 interrupt request bit INT1/ZCR interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request Serial I/O 1 interrupt request bit Serial I/O automatic transfer interrupt request bit q q T T T T 4 5 6 7 0 0 0 0 Serial I/O 2 interrupt request bit Timer 1 interrupt request bit 0 : No interrupt request 1 : Interrupt request Serial I/O 3 interrupt request bit Timer 2 interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request T T T T T "0" is set by software, but not "1." INT2 interrupt request bit Remote control/counter overflow interrupt request bit q q Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At reset RW 0 1 2 3 0 0 0 0 Interrupt control register 1 (ICON1) [Address:3E16] Name INT0 interrupt enable bit INT1/ZCR interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 4 5 6 7 0 0 0 0 Serial I/O 2 interrupt enable bit Timer 1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Serial I/O 3 interrupt enable bit Timer 2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Serial I/O 1 interrupt enable bit Serial I/O automatic transfer interrupt enable bit q q INT2 interrupt enable bit Remote control/counter overflow interrupt enable bit q q 0 : No interrupt request 1 : Interrupt request |
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